rtc_pl031.cc revision 9806:3f262c18ad5d 
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "base/intmath.hh"
41#include "base/time.hh"
42#include "base/trace.hh"
43#include "debug/Checkpoint.hh"
44#include "debug/Timer.hh"
45#include "dev/arm/amba_device.hh"
46#include "dev/arm/rtc_pl031.hh"
47#include "dev/mc146818.hh"
48#include "mem/packet.hh"
49#include "mem/packet_access.hh"
50
51PL031::PL031(Params *p)
52    : AmbaIntDevice(p), timeVal(mkutctime(&p->time)), lastWrittenTick(0),
53            loadVal(0), matchVal(0), rawInt(false), maskInt(false),
54            pendingInt(false), matchEvent(this)
55{
56    pioSize = 0xfff;
57}
58
59
60Tick
61PL031::read(PacketPtr pkt)
62{
63    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
64    assert(pkt->getSize() == 4);
65    Addr daddr = pkt->getAddr() - pioAddr;
66    pkt->allocate();
67    uint32_t data;
68
69    DPRINTF(Timer, "Reading from RTC at offset: %#x\n", daddr);
70
71    switch (daddr) {
72      case DataReg:
73        data = timeVal + ((curTick() - lastWrittenTick) / SimClock::Int::s);
74        break;
75      case MatchReg:
76        data = matchVal;
77        break;
78      case LoadReg:
79        data = loadVal;
80        break;
81      case ControlReg:
82        data = 1; // Always enabled otherwise there is no point
83        break;
84      case IntMask:
85        data = maskInt;
86        break;
87      case RawISR:
88        data = rawInt;
89        break;
90      case MaskedISR:
91        data = pendingInt;
92        break;
93      default:
94        if (readId(pkt, ambaId, pioAddr)) {
95            // Hack for variable sized access
96            data = pkt->get<uint32_t>();
97            break;
98        }
99        panic("Tried to read PL031 at offset %#x that doesn't exist\n", daddr);
100        break;
101    }
102
103    switch(pkt->getSize()) {
104      case 1:
105        pkt->set<uint8_t>(data);
106        break;
107      case 2:
108        pkt->set<uint16_t>(data);
109        break;
110      case 4:
111        pkt->set<uint32_t>(data);
112        break;
113      default:
114        panic("Uart read size too big?\n");
115        break;
116    }
117
118
119    pkt->makeAtomicResponse();
120    return pioDelay;
121}
122
123Tick
124PL031::write(PacketPtr pkt)
125{
126    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
127    assert(pkt->getSize() == 4);
128    Addr daddr = pkt->getAddr() - pioAddr;
129    pkt->allocate();
130    DPRINTF(Timer, "Writing to RTC at offset: %#x\n", daddr);
131
132    switch (daddr) {
133      case DataReg:
134        break;
135      case MatchReg:
136        matchVal = pkt->get<uint32_t>();
137        resyncMatch();
138        break;
139      case LoadReg:
140        lastWrittenTick = curTick();
141        timeVal = pkt->get<uint32_t>();
142        loadVal = timeVal;
143        resyncMatch();
144        break;
145      case ControlReg:
146        break; // Can't stop when started
147      case IntMask:
148        maskInt = pkt->get<uint32_t>();
149        break;
150      case IntClear:
151        if (pkt->get<uint32_t>()) {
152            rawInt = false;
153            pendingInt = false;
154        }
155        break;
156      default:
157        if (readId(pkt, ambaId, pioAddr))
158            break;
159        panic("Tried to read PL031 at offset %#x that doesn't exist\n", daddr);
160        break;
161    }
162
163    pkt->makeAtomicResponse();
164    return pioDelay;
165}
166
167void
168PL031::resyncMatch()
169{
170    DPRINTF(Timer, "Setting up new match event match=%d time=%d\n", matchVal,
171            timeVal);
172
173    uint32_t seconds_until = matchVal - timeVal;
174    Tick ticks_until = SimClock::Int::s * seconds_until;
175
176    if (matchEvent.scheduled()) {
177        DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n");
178        deschedule(matchEvent);
179    }
180    schedule(matchEvent, curTick() + ticks_until);
181    DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick() + ticks_until);
182}
183
184void
185PL031::counterMatch()
186{
187    DPRINTF(Timer, "Counter reached zero\n");
188
189    rawInt = true;
190    bool old_pending = pendingInt;
191    pendingInt = maskInt & rawInt;
192    if (pendingInt && !old_pending) {
193        DPRINTF(Timer, "-- Causing interrupt\n");
194        gic->sendInt(intNum);
195    }
196}
197
198void
199PL031::serialize(std::ostream &os)
200{
201    DPRINTF(Checkpoint, "Serializing Arm PL031\n");
202    SERIALIZE_SCALAR(timeVal);
203    SERIALIZE_SCALAR(lastWrittenTick);
204    SERIALIZE_SCALAR(loadVal);
205    SERIALIZE_SCALAR(matchVal);
206    SERIALIZE_SCALAR(rawInt);
207    SERIALIZE_SCALAR(maskInt);
208    SERIALIZE_SCALAR(pendingInt);
209
210    bool is_in_event = matchEvent.scheduled();
211    SERIALIZE_SCALAR(is_in_event);
212
213    Tick event_time;
214    if (is_in_event){
215        event_time = matchEvent.when();
216        SERIALIZE_SCALAR(event_time);
217    }
218}
219
220void
221PL031::unserialize(Checkpoint *cp, const std::string &section)
222{
223    DPRINTF(Checkpoint, "Unserializing Arm PL031\n");
224
225    UNSERIALIZE_SCALAR(timeVal);
226    UNSERIALIZE_SCALAR(lastWrittenTick);
227    UNSERIALIZE_SCALAR(loadVal);
228    UNSERIALIZE_SCALAR(matchVal);
229    UNSERIALIZE_SCALAR(rawInt);
230    UNSERIALIZE_SCALAR(maskInt);
231    UNSERIALIZE_SCALAR(pendingInt);
232
233    bool is_in_event;
234    UNSERIALIZE_SCALAR(is_in_event);
235
236    Tick event_time;
237    if (is_in_event){
238        UNSERIALIZE_SCALAR(event_time);
239        schedule(matchEvent, event_time);
240    }
241}
242
243
244
245PL031 *
246PL031Params::create()
247{
248    return new PL031(this);
249}
250