rtc_pl031.cc revision 10905 
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "base/intmath.hh"
41#include "base/time.hh"
42#include "base/trace.hh"
43#include "debug/Checkpoint.hh"
44#include "debug/Timer.hh"
45#include "dev/arm/amba_device.hh"
46#include "dev/arm/rtc_pl031.hh"
47#include "mem/packet.hh"
48#include "mem/packet_access.hh"
49
50PL031::PL031(Params *p)
51    : AmbaIntDevice(p, 0xfff), timeVal(mkutctime(&p->time)),
52      lastWrittenTick(0), loadVal(0), matchVal(0),
53      rawInt(false), maskInt(false), pendingInt(false), matchEvent(this)
54{
55}
56
57
58Tick
59PL031::read(PacketPtr pkt)
60{
61    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
62    assert(pkt->getSize() == 4);
63    Addr daddr = pkt->getAddr() - pioAddr;
64    uint32_t data;
65
66    DPRINTF(Timer, "Reading from RTC at offset: %#x\n", daddr);
67
68    switch (daddr) {
69      case DataReg:
70        data = timeVal + ((curTick() - lastWrittenTick) / SimClock::Int::s);
71        break;
72      case MatchReg:
73        data = matchVal;
74        break;
75      case LoadReg:
76        data = loadVal;
77        break;
78      case ControlReg:
79        data = 1; // Always enabled otherwise there is no point
80        break;
81      case IntMask:
82        data = maskInt;
83        break;
84      case RawISR:
85        data = rawInt;
86        break;
87      case MaskedISR:
88        data = pendingInt;
89        break;
90      default:
91        if (readId(pkt, ambaId, pioAddr)) {
92            // Hack for variable sized access
93            data = pkt->get<uint32_t>();
94            break;
95        }
96        panic("Tried to read PL031 at offset %#x that doesn't exist\n", daddr);
97        break;
98    }
99
100    switch(pkt->getSize()) {
101      case 1:
102        pkt->set<uint8_t>(data);
103        break;
104      case 2:
105        pkt->set<uint16_t>(data);
106        break;
107      case 4:
108        pkt->set<uint32_t>(data);
109        break;
110      default:
111        panic("Uart read size too big?\n");
112        break;
113    }
114
115
116    pkt->makeAtomicResponse();
117    return pioDelay;
118}
119
120Tick
121PL031::write(PacketPtr pkt)
122{
123    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
124    assert(pkt->getSize() == 4);
125    Addr daddr = pkt->getAddr() - pioAddr;
126    DPRINTF(Timer, "Writing to RTC at offset: %#x\n", daddr);
127
128    switch (daddr) {
129      case DataReg:
130        break;
131      case MatchReg:
132        matchVal = pkt->get<uint32_t>();
133        resyncMatch();
134        break;
135      case LoadReg:
136        lastWrittenTick = curTick();
137        timeVal = pkt->get<uint32_t>();
138        loadVal = timeVal;
139        resyncMatch();
140        break;
141      case ControlReg:
142        break; // Can't stop when started
143      case IntMask:
144        maskInt = pkt->get<uint32_t>();
145        break;
146      case IntClear:
147        if (pkt->get<uint32_t>()) {
148            rawInt = false;
149            pendingInt = false;
150        }
151        break;
152      default:
153        if (readId(pkt, ambaId, pioAddr))
154            break;
155        panic("Tried to read PL031 at offset %#x that doesn't exist\n", daddr);
156        break;
157    }
158
159    pkt->makeAtomicResponse();
160    return pioDelay;
161}
162
163void
164PL031::resyncMatch()
165{
166    DPRINTF(Timer, "Setting up new match event match=%d time=%d\n", matchVal,
167            timeVal);
168
169    uint32_t seconds_until = matchVal - timeVal;
170    Tick ticks_until = SimClock::Int::s * seconds_until;
171
172    if (matchEvent.scheduled()) {
173        DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n");
174        deschedule(matchEvent);
175    }
176    schedule(matchEvent, curTick() + ticks_until);
177    DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick() + ticks_until);
178}
179
180void
181PL031::counterMatch()
182{
183    DPRINTF(Timer, "Counter reached zero\n");
184
185    rawInt = true;
186    bool old_pending = pendingInt;
187    pendingInt = maskInt & rawInt;
188    if (pendingInt && !old_pending) {
189        DPRINTF(Timer, "-- Causing interrupt\n");
190        gic->sendInt(intNum);
191    }
192}
193
194void
195PL031::serialize(CheckpointOut &cp) const
196{
197    DPRINTF(Checkpoint, "Serializing Arm PL031\n");
198    SERIALIZE_SCALAR(timeVal);
199    SERIALIZE_SCALAR(lastWrittenTick);
200    SERIALIZE_SCALAR(loadVal);
201    SERIALIZE_SCALAR(matchVal);
202    SERIALIZE_SCALAR(rawInt);
203    SERIALIZE_SCALAR(maskInt);
204    SERIALIZE_SCALAR(pendingInt);
205
206    bool is_in_event = matchEvent.scheduled();
207    SERIALIZE_SCALAR(is_in_event);
208
209    Tick event_time;
210    if (is_in_event){
211        event_time = matchEvent.when();
212        SERIALIZE_SCALAR(event_time);
213    }
214}
215
216void
217PL031::unserialize(CheckpointIn &cp)
218{
219    DPRINTF(Checkpoint, "Unserializing Arm PL031\n");
220
221    UNSERIALIZE_SCALAR(timeVal);
222    UNSERIALIZE_SCALAR(lastWrittenTick);
223    UNSERIALIZE_SCALAR(loadVal);
224    UNSERIALIZE_SCALAR(matchVal);
225    UNSERIALIZE_SCALAR(rawInt);
226    UNSERIALIZE_SCALAR(maskInt);
227    UNSERIALIZE_SCALAR(pendingInt);
228
229    bool is_in_event;
230    UNSERIALIZE_SCALAR(is_in_event);
231
232    Tick event_time;
233    if (is_in_event){
234        UNSERIALIZE_SCALAR(event_time);
235        schedule(matchEvent, event_time);
236    }
237}
238
239
240
241PL031 *
242PL031Params::create()
243{
244    return new PL031(this);
245}
246