realview.cc revision 5034
16876Ssteve.reinhardt@amd.com/*
26876Ssteve.reinhardt@amd.com * Copyright (c) 2004-2005 The Regents of The University of Michigan
36876Ssteve.reinhardt@amd.com * All rights reserved.
46876Ssteve.reinhardt@amd.com *
56876Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without
66876Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are
76876Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright
86876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer;
96876Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright
106876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the
116876Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution;
126876Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its
136876Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from
146876Ssteve.reinhardt@amd.com * this software without specific prior written permission.
156876Ssteve.reinhardt@amd.com *
166876Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
176876Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
186876Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
196876Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
206876Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
216876Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
226876Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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246876Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
256876Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
266876Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
276876Ssteve.reinhardt@amd.com *
286876Ssteve.reinhardt@amd.com * Authors: Ali Saidi
297039Snate@binkert.org */
307039Snate@binkert.org
316285Snate@binkert.org/** @file
327039Snate@binkert.org * Implementation of T1000 platform.
336285Snate@binkert.org */
346285Snate@binkert.org
356922SBrad.Beckmann@amd.com#include <deque>
368092Snilay@cs.wisc.edu#include <string>
377909Shestness@cs.utexas.edu#include <vector>
388229Snate@binkert.org
398229Snate@binkert.org#include "cpu/intr_control.hh"
407039Snate@binkert.org#include "dev/simconsole.hh"
416876Ssteve.reinhardt@amd.com#include "dev/sparc/t1000.hh"
426876Ssteve.reinhardt@amd.com#include "sim/system.hh"
436876Ssteve.reinhardt@amd.com
446876Ssteve.reinhardt@amd.comusing namespace std;
456876Ssteve.reinhardt@amd.com//Should this be AlphaISA?
467039Snate@binkert.orgusing namespace TheISA;
477039Snate@binkert.org
487039Snate@binkert.orgT1000::T1000(const Params *p)
496882SBrad.Beckmann@amd.com    : Platform(p), system(p->system)
506882SBrad.Beckmann@amd.com{
517039Snate@binkert.org    // set the back pointer from the system to myself
526882SBrad.Beckmann@amd.com    system->platform = this;
537910SBrad.Beckmann@amd.com}
547915SBrad.Beckmann@amd.com
556882SBrad.Beckmann@amd.comTick
566882SBrad.Beckmann@amd.comT1000::intrFrequency()
577915SBrad.Beckmann@amd.com{
587915SBrad.Beckmann@amd.com    panic("Need implementation\n");
596882SBrad.Beckmann@amd.com    M5_DUMMY_RETURN
606882SBrad.Beckmann@amd.com}
617909Shestness@cs.utexas.edu
627910SBrad.Beckmann@amd.comvoid
637910SBrad.Beckmann@amd.comT1000::postConsoleInt()
647910SBrad.Beckmann@amd.com{
657910SBrad.Beckmann@amd.com    warn_once("Don't know what interrupt to post for console.\n");
667910SBrad.Beckmann@amd.com    //panic("Need implementation\n");
677910SBrad.Beckmann@amd.com}
686882SBrad.Beckmann@amd.com
696882SBrad.Beckmann@amd.comvoid
706882SBrad.Beckmann@amd.comT1000::clearConsoleInt()
716882SBrad.Beckmann@amd.com{
726882SBrad.Beckmann@amd.com    warn_once("Don't know what interrupt to clear for console.\n");
736882SBrad.Beckmann@amd.com    //panic("Need implementation\n");
746882SBrad.Beckmann@amd.com}
756882SBrad.Beckmann@amd.com
766882SBrad.Beckmann@amd.comvoid
776882SBrad.Beckmann@amd.comT1000::postPciInt(int line)
786882SBrad.Beckmann@amd.com{
796882SBrad.Beckmann@amd.com    panic("Need implementation\n");
806882SBrad.Beckmann@amd.com}
817039Snate@binkert.org
826882SBrad.Beckmann@amd.comvoid
836882SBrad.Beckmann@amd.comT1000::clearPciInt(int line)
846882SBrad.Beckmann@amd.com{
857039Snate@binkert.org    panic("Need implementation\n");
866882SBrad.Beckmann@amd.com}
876882SBrad.Beckmann@amd.com
886882SBrad.Beckmann@amd.comAddr
896882SBrad.Beckmann@amd.comT1000::pciToDma(Addr pciAddr) const
906882SBrad.Beckmann@amd.com{
916882SBrad.Beckmann@amd.com    panic("Need implementation\n");
926882SBrad.Beckmann@amd.com    M5_DUMMY_RETURN
936882SBrad.Beckmann@amd.com}
946882SBrad.Beckmann@amd.com
956882SBrad.Beckmann@amd.com
966882SBrad.Beckmann@amd.comAddr
976882SBrad.Beckmann@amd.comT1000::calcConfigAddr(int bus, int dev, int func)
986882SBrad.Beckmann@amd.com{
996882SBrad.Beckmann@amd.com    panic("Need implementation\n");
1007039Snate@binkert.org    M5_DUMMY_RETURN
1016882SBrad.Beckmann@amd.com}
1026882SBrad.Beckmann@amd.com
1036882SBrad.Beckmann@amd.comT1000 *
1046882SBrad.Beckmann@amd.comT1000Params::create()
1056876Ssteve.reinhardt@amd.com{
1066876Ssteve.reinhardt@amd.com    return new T1000(this);
1076882SBrad.Beckmann@amd.com}
1086882SBrad.Beckmann@amd.com