pl111.hh revision 9415
17753SWilliam.Wang@arm.com/* 29395SAndreas.Sandberg@ARM.com * Copyright (c) 2010-2012 ARM Limited 37753SWilliam.Wang@arm.com * All rights reserved 47753SWilliam.Wang@arm.com * 57753SWilliam.Wang@arm.com * The license below extends only to copyright in the software and shall 67753SWilliam.Wang@arm.com * not be construed as granting a license to any other intellectual 77753SWilliam.Wang@arm.com * property including but not limited to intellectual property relating 87753SWilliam.Wang@arm.com * to a hardware implementation of the functionality of the software 97753SWilliam.Wang@arm.com * licensed hereunder. You may use the software subject to the license 107753SWilliam.Wang@arm.com * terms below provided that you ensure that this notice is replicated 117753SWilliam.Wang@arm.com * unmodified and in its entirety in all distributions of the software, 127753SWilliam.Wang@arm.com * modified or unmodified, in source code or in binary form. 137753SWilliam.Wang@arm.com * 147753SWilliam.Wang@arm.com * Redistribution and use in source and binary forms, with or without 157753SWilliam.Wang@arm.com * modification, are permitted provided that the following conditions are 167753SWilliam.Wang@arm.com * met: redistributions of source code must retain the above copyright 177753SWilliam.Wang@arm.com * notice, this list of conditions and the following disclaimer; 187753SWilliam.Wang@arm.com * redistributions in binary form must reproduce the above copyright 197753SWilliam.Wang@arm.com * notice, this list of conditions and the following disclaimer in the 207753SWilliam.Wang@arm.com * documentation and/or other materials provided with the distribution; 217753SWilliam.Wang@arm.com * neither the name of the copyright holders nor the names of its 227753SWilliam.Wang@arm.com * contributors may be used to endorse or promote products derived from 237753SWilliam.Wang@arm.com * this software without specific prior written permission. 247753SWilliam.Wang@arm.com * 257753SWilliam.Wang@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267753SWilliam.Wang@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277753SWilliam.Wang@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287753SWilliam.Wang@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297753SWilliam.Wang@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307753SWilliam.Wang@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317753SWilliam.Wang@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327753SWilliam.Wang@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337753SWilliam.Wang@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347753SWilliam.Wang@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357753SWilliam.Wang@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367753SWilliam.Wang@arm.com * 377753SWilliam.Wang@arm.com * Authors: William Wang 387950SAli.Saidi@ARM.com * Ali Saidi 397753SWilliam.Wang@arm.com */ 407753SWilliam.Wang@arm.com 417753SWilliam.Wang@arm.com 427753SWilliam.Wang@arm.com/** @file 437753SWilliam.Wang@arm.com * Implementiation of a PL111 CLCD controller 447753SWilliam.Wang@arm.com */ 457753SWilliam.Wang@arm.com 467753SWilliam.Wang@arm.com#ifndef __DEV_ARM_PL111_HH__ 477753SWilliam.Wang@arm.com#define __DEV_ARM_PL111_HH__ 487753SWilliam.Wang@arm.com 497753SWilliam.Wang@arm.com#include <fstream> 507753SWilliam.Wang@arm.com 517753SWilliam.Wang@arm.com#include "dev/arm/amba_device.hh" 527753SWilliam.Wang@arm.com#include "params/Pl111.hh" 537753SWilliam.Wang@arm.com#include "sim/serialize.hh" 547753SWilliam.Wang@arm.com 557753SWilliam.Wang@arm.comclass Gic; 569330Schander.sudanthi@arm.comclass VncInput; 577950SAli.Saidi@ARM.comclass Bitmap; 587753SWilliam.Wang@arm.com 597753SWilliam.Wang@arm.comclass Pl111: public AmbaDmaDevice 607753SWilliam.Wang@arm.com{ 617753SWilliam.Wang@arm.com protected: 627753SWilliam.Wang@arm.com static const uint64_t AMBA_ID = ULL(0xb105f00d00141111); 637753SWilliam.Wang@arm.com /** ARM PL111 register map*/ 647753SWilliam.Wang@arm.com static const int LcdTiming0 = 0x000; 657753SWilliam.Wang@arm.com static const int LcdTiming1 = 0x004; 667753SWilliam.Wang@arm.com static const int LcdTiming2 = 0x008; 677753SWilliam.Wang@arm.com static const int LcdTiming3 = 0x00C; 687753SWilliam.Wang@arm.com static const int LcdUpBase = 0x010; 697753SWilliam.Wang@arm.com static const int LcdLpBase = 0x014; 707753SWilliam.Wang@arm.com static const int LcdControl = 0x018; 717753SWilliam.Wang@arm.com static const int LcdImsc = 0x01C; 727753SWilliam.Wang@arm.com static const int LcdRis = 0x020; 737753SWilliam.Wang@arm.com static const int LcdMis = 0x024; 747753SWilliam.Wang@arm.com static const int LcdIcr = 0x028; 757753SWilliam.Wang@arm.com static const int LcdUpCurr = 0x02C; 767753SWilliam.Wang@arm.com static const int LcdLpCurr = 0x030; 777753SWilliam.Wang@arm.com static const int LcdPalette = 0x200; 787753SWilliam.Wang@arm.com static const int CrsrImage = 0x800; 797753SWilliam.Wang@arm.com static const int ClcdCrsrCtrl = 0xC00; 807753SWilliam.Wang@arm.com static const int ClcdCrsrConfig = 0xC04; 817753SWilliam.Wang@arm.com static const int ClcdCrsrPalette0 = 0xC08; 827753SWilliam.Wang@arm.com static const int ClcdCrsrPalette1 = 0xC0C; 837753SWilliam.Wang@arm.com static const int ClcdCrsrXY = 0xC10; 847753SWilliam.Wang@arm.com static const int ClcdCrsrClip = 0xC14; 857753SWilliam.Wang@arm.com static const int ClcdCrsrImsc = 0xC20; 867753SWilliam.Wang@arm.com static const int ClcdCrsrIcr = 0xC24; 877753SWilliam.Wang@arm.com static const int ClcdCrsrRis = 0xC28; 887753SWilliam.Wang@arm.com static const int ClcdCrsrMis = 0xC2C; 897753SWilliam.Wang@arm.com 907753SWilliam.Wang@arm.com static const int LcdPaletteSize = 128; 917753SWilliam.Wang@arm.com static const int CrsrImageSize = 256; 927753SWilliam.Wang@arm.com 937753SWilliam.Wang@arm.com static const int LcdMaxWidth = 1024; // pixels per line 947753SWilliam.Wang@arm.com static const int LcdMaxHeight = 768; // lines per panel 957753SWilliam.Wang@arm.com 967753SWilliam.Wang@arm.com static const int dmaSize = 8; // 64 bits 977753SWilliam.Wang@arm.com static const int maxOutstandingDma = 16; // 16 deep FIFO of 64 bits 987753SWilliam.Wang@arm.com 999415SChander.Sudanthi@arm.com static const int buffer_size = LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t); 1009415SChander.Sudanthi@arm.com 1017950SAli.Saidi@ARM.com enum LcdMode { 1027950SAli.Saidi@ARM.com bpp1 = 0, 1037950SAli.Saidi@ARM.com bpp2, 1047950SAli.Saidi@ARM.com bpp4, 1057950SAli.Saidi@ARM.com bpp8, 1067950SAli.Saidi@ARM.com bpp16, 1077950SAli.Saidi@ARM.com bpp24, 1087950SAli.Saidi@ARM.com bpp16m565, 1097950SAli.Saidi@ARM.com bpp12 1107950SAli.Saidi@ARM.com }; 1117950SAli.Saidi@ARM.com 1127753SWilliam.Wang@arm.com BitUnion8(InterruptReg) 1137950SAli.Saidi@ARM.com Bitfield<1> underflow; 1147950SAli.Saidi@ARM.com Bitfield<2> baseaddr; 1157950SAli.Saidi@ARM.com Bitfield<3> vcomp; 1167950SAli.Saidi@ARM.com Bitfield<4> ahbmaster; 1177753SWilliam.Wang@arm.com EndBitUnion(InterruptReg) 1187753SWilliam.Wang@arm.com 1197753SWilliam.Wang@arm.com BitUnion32(TimingReg0) 1207950SAli.Saidi@ARM.com Bitfield<7,2> ppl; 1217950SAli.Saidi@ARM.com Bitfield<15,8> hsw; 1227950SAli.Saidi@ARM.com Bitfield<23,16> hfp; 1237950SAli.Saidi@ARM.com Bitfield<31,24> hbp; 1247753SWilliam.Wang@arm.com EndBitUnion(TimingReg0) 1257753SWilliam.Wang@arm.com 1267753SWilliam.Wang@arm.com BitUnion32(TimingReg1) 1277950SAli.Saidi@ARM.com Bitfield<9,0> lpp; 1287950SAli.Saidi@ARM.com Bitfield<15,10> vsw; 1297950SAli.Saidi@ARM.com Bitfield<23,16> vfp; 1307950SAli.Saidi@ARM.com Bitfield<31,24> vbp; 1317753SWilliam.Wang@arm.com EndBitUnion(TimingReg1) 1327753SWilliam.Wang@arm.com 1337753SWilliam.Wang@arm.com BitUnion32(TimingReg2) 1347950SAli.Saidi@ARM.com Bitfield<4,0> pcdlo; 1357950SAli.Saidi@ARM.com Bitfield<5> clksel; 1367950SAli.Saidi@ARM.com Bitfield<10,6> acb; 1377950SAli.Saidi@ARM.com Bitfield<11> avs; 1387950SAli.Saidi@ARM.com Bitfield<12> ihs; 1397950SAli.Saidi@ARM.com Bitfield<13> ipc; 1407950SAli.Saidi@ARM.com Bitfield<14> ioe; 1417950SAli.Saidi@ARM.com Bitfield<25,16> cpl; 1427950SAli.Saidi@ARM.com Bitfield<26> bcd; 1437950SAli.Saidi@ARM.com Bitfield<31,27> pcdhi; 1447753SWilliam.Wang@arm.com EndBitUnion(TimingReg2) 1457753SWilliam.Wang@arm.com 1467753SWilliam.Wang@arm.com BitUnion32(TimingReg3) 1477950SAli.Saidi@ARM.com Bitfield<6,0> led; 1487950SAli.Saidi@ARM.com Bitfield<16> lee; 1497753SWilliam.Wang@arm.com EndBitUnion(TimingReg3) 1507753SWilliam.Wang@arm.com 1517753SWilliam.Wang@arm.com BitUnion32(ControlReg) 1527950SAli.Saidi@ARM.com Bitfield<0> lcden; 1537950SAli.Saidi@ARM.com Bitfield<3,1> lcdbpp; 1547950SAli.Saidi@ARM.com Bitfield<4> lcdbw; 1557950SAli.Saidi@ARM.com Bitfield<5> lcdtft; 1567950SAli.Saidi@ARM.com Bitfield<6> lcdmono8; 1577950SAli.Saidi@ARM.com Bitfield<7> lcddual; 1587950SAli.Saidi@ARM.com Bitfield<8> bgr; 1597950SAli.Saidi@ARM.com Bitfield<9> bebo; 1607950SAli.Saidi@ARM.com Bitfield<10> bepo; 1617950SAli.Saidi@ARM.com Bitfield<11> lcdpwr; 1627950SAli.Saidi@ARM.com Bitfield<13,12> lcdvcomp; 1637950SAli.Saidi@ARM.com Bitfield<16> watermark; 1647753SWilliam.Wang@arm.com EndBitUnion(ControlReg) 1657753SWilliam.Wang@arm.com 1669395SAndreas.Sandberg@ARM.com /** 1679395SAndreas.Sandberg@ARM.com * Event wrapper for dmaDone() 1689395SAndreas.Sandberg@ARM.com * 1699395SAndreas.Sandberg@ARM.com * This event calls pushes its this pointer onto the freeDoneEvent 1709395SAndreas.Sandberg@ARM.com * vector and calls dmaDone() when triggered. 1719395SAndreas.Sandberg@ARM.com */ 1729395SAndreas.Sandberg@ARM.com class DmaDoneEvent : public Event 1739395SAndreas.Sandberg@ARM.com { 1749395SAndreas.Sandberg@ARM.com private: 1759395SAndreas.Sandberg@ARM.com Pl111 &obj; 1769395SAndreas.Sandberg@ARM.com 1779395SAndreas.Sandberg@ARM.com public: 1789395SAndreas.Sandberg@ARM.com DmaDoneEvent(Pl111 *_obj) 1799395SAndreas.Sandberg@ARM.com : Event(), obj(*_obj) {} 1809395SAndreas.Sandberg@ARM.com 1819395SAndreas.Sandberg@ARM.com void process() { 1829395SAndreas.Sandberg@ARM.com obj.dmaDoneEventFree.push_back(this); 1839395SAndreas.Sandberg@ARM.com obj.dmaDone(); 1849395SAndreas.Sandberg@ARM.com } 1859395SAndreas.Sandberg@ARM.com 1869395SAndreas.Sandberg@ARM.com const std::string name() const { 1879395SAndreas.Sandberg@ARM.com return obj.name() + ".DmaDoneEvent"; 1889395SAndreas.Sandberg@ARM.com } 1899395SAndreas.Sandberg@ARM.com }; 1909395SAndreas.Sandberg@ARM.com 1917753SWilliam.Wang@arm.com /** Horizontal axis panel control register */ 1927753SWilliam.Wang@arm.com TimingReg0 lcdTiming0; 1937753SWilliam.Wang@arm.com 1947753SWilliam.Wang@arm.com /** Vertical axis panel control register */ 1957753SWilliam.Wang@arm.com TimingReg1 lcdTiming1; 1967753SWilliam.Wang@arm.com 1977753SWilliam.Wang@arm.com /** Clock and signal polarity control register */ 1987753SWilliam.Wang@arm.com TimingReg2 lcdTiming2; 1997753SWilliam.Wang@arm.com 2007753SWilliam.Wang@arm.com /** Line end control register */ 2017753SWilliam.Wang@arm.com TimingReg3 lcdTiming3; 2027753SWilliam.Wang@arm.com 2037753SWilliam.Wang@arm.com /** Upper panel frame base address register */ 2047753SWilliam.Wang@arm.com int lcdUpbase; 2057753SWilliam.Wang@arm.com 2067753SWilliam.Wang@arm.com /** Lower panel frame base address register */ 2077753SWilliam.Wang@arm.com int lcdLpbase; 2087753SWilliam.Wang@arm.com 2097753SWilliam.Wang@arm.com /** Control register */ 2107753SWilliam.Wang@arm.com ControlReg lcdControl; 2117753SWilliam.Wang@arm.com 2127753SWilliam.Wang@arm.com /** Interrupt mask set/clear register */ 2137753SWilliam.Wang@arm.com InterruptReg lcdImsc; 2147753SWilliam.Wang@arm.com 2157753SWilliam.Wang@arm.com /** Raw interrupt status register - const */ 2167753SWilliam.Wang@arm.com InterruptReg lcdRis; 2177753SWilliam.Wang@arm.com 2187753SWilliam.Wang@arm.com /** Masked interrupt status register */ 2197753SWilliam.Wang@arm.com InterruptReg lcdMis; 2207753SWilliam.Wang@arm.com 2217753SWilliam.Wang@arm.com /** 256x16-bit color palette registers 2227753SWilliam.Wang@arm.com * 256 palette entries organized as 128 locations of two entries per word */ 2237753SWilliam.Wang@arm.com int lcdPalette[LcdPaletteSize]; 2247753SWilliam.Wang@arm.com 2257753SWilliam.Wang@arm.com /** Cursor image RAM register 2267753SWilliam.Wang@arm.com * 256-word wide values defining images overlaid by the hw cursor mechanism */ 2277753SWilliam.Wang@arm.com int cursorImage[CrsrImageSize]; 2287753SWilliam.Wang@arm.com 2297753SWilliam.Wang@arm.com /** Cursor control register */ 2307753SWilliam.Wang@arm.com int clcdCrsrCtrl; 2317753SWilliam.Wang@arm.com 2327753SWilliam.Wang@arm.com /** Cursor configuration register */ 2337753SWilliam.Wang@arm.com int clcdCrsrConfig; 2347753SWilliam.Wang@arm.com 2357753SWilliam.Wang@arm.com /** Cursor palette registers */ 2367753SWilliam.Wang@arm.com int clcdCrsrPalette0; 2377753SWilliam.Wang@arm.com int clcdCrsrPalette1; 2387753SWilliam.Wang@arm.com 2397753SWilliam.Wang@arm.com /** Cursor XY position register */ 2407753SWilliam.Wang@arm.com int clcdCrsrXY; 2417753SWilliam.Wang@arm.com 2427753SWilliam.Wang@arm.com /** Cursor clip position register */ 2437753SWilliam.Wang@arm.com int clcdCrsrClip; 2447753SWilliam.Wang@arm.com 2457753SWilliam.Wang@arm.com /** Cursor interrupt mask set/clear register */ 2467753SWilliam.Wang@arm.com InterruptReg clcdCrsrImsc; 2477753SWilliam.Wang@arm.com 2487753SWilliam.Wang@arm.com /** Cursor interrupt clear register */ 2497753SWilliam.Wang@arm.com InterruptReg clcdCrsrIcr; 2507753SWilliam.Wang@arm.com 2517753SWilliam.Wang@arm.com /** Cursor raw interrupt status register - const */ 2527753SWilliam.Wang@arm.com InterruptReg clcdCrsrRis; 2537753SWilliam.Wang@arm.com 2547753SWilliam.Wang@arm.com /** Cursor masked interrupt status register - const */ 2557753SWilliam.Wang@arm.com InterruptReg clcdCrsrMis; 2567753SWilliam.Wang@arm.com 2579394Sandreas.hansson@arm.com /** Pixel clock */ 2589394Sandreas.hansson@arm.com Tick pixelClock; 2599394Sandreas.hansson@arm.com 2607950SAli.Saidi@ARM.com /** VNC server */ 2619330Schander.sudanthi@arm.com VncInput *vnc; 2627950SAli.Saidi@ARM.com 2637950SAli.Saidi@ARM.com /** Helper to write out bitmaps */ 2647950SAli.Saidi@ARM.com Bitmap *bmp; 2657950SAli.Saidi@ARM.com 2667950SAli.Saidi@ARM.com /** Picture of what the current frame buffer looks like */ 2677950SAli.Saidi@ARM.com std::ostream *pic; 2687753SWilliam.Wang@arm.com 2697753SWilliam.Wang@arm.com /** Frame buffer width - pixels per line */ 2707753SWilliam.Wang@arm.com uint16_t width; 2717753SWilliam.Wang@arm.com 2727950SAli.Saidi@ARM.com /** Frame buffer height - lines per panel */ 2737950SAli.Saidi@ARM.com uint16_t height; 2747950SAli.Saidi@ARM.com 2757950SAli.Saidi@ARM.com /** Bytes per pixel */ 2767950SAli.Saidi@ARM.com uint8_t bytesPerPixel; 2777950SAli.Saidi@ARM.com 2787753SWilliam.Wang@arm.com /** CLCDC supports up to 1024x768 */ 2797950SAli.Saidi@ARM.com uint8_t *dmaBuffer; 2807753SWilliam.Wang@arm.com 2817753SWilliam.Wang@arm.com /** Start time for frame buffer dma read */ 2827753SWilliam.Wang@arm.com Tick startTime; 2837753SWilliam.Wang@arm.com 2847753SWilliam.Wang@arm.com /** Frame buffer base address */ 2857753SWilliam.Wang@arm.com Addr startAddr; 2867753SWilliam.Wang@arm.com 2877753SWilliam.Wang@arm.com /** Frame buffer max address */ 2887753SWilliam.Wang@arm.com Addr maxAddr; 2897753SWilliam.Wang@arm.com 2907753SWilliam.Wang@arm.com /** Frame buffer current address */ 2917753SWilliam.Wang@arm.com Addr curAddr; 2927753SWilliam.Wang@arm.com 2937753SWilliam.Wang@arm.com /** DMA FIFO watermark */ 2947753SWilliam.Wang@arm.com int waterMark; 2957753SWilliam.Wang@arm.com 2967753SWilliam.Wang@arm.com /** Number of pending dma reads */ 2977753SWilliam.Wang@arm.com int dmaPendingNum; 2987753SWilliam.Wang@arm.com 2997950SAli.Saidi@ARM.com /** Send updated parameters to the vnc server */ 3007950SAli.Saidi@ARM.com void updateVideoParams(); 3017950SAli.Saidi@ARM.com 3027753SWilliam.Wang@arm.com /** DMA framebuffer read */ 3037753SWilliam.Wang@arm.com void readFramebuffer(); 3047753SWilliam.Wang@arm.com 3057753SWilliam.Wang@arm.com /** Generate dma framebuffer read event */ 3067753SWilliam.Wang@arm.com void generateReadEvent(); 3077753SWilliam.Wang@arm.com 3087753SWilliam.Wang@arm.com /** Function to generate interrupt */ 3097753SWilliam.Wang@arm.com void generateInterrupt(); 3107753SWilliam.Wang@arm.com 3117753SWilliam.Wang@arm.com /** fillFIFO event */ 3127753SWilliam.Wang@arm.com void fillFifo(); 3137753SWilliam.Wang@arm.com 3147950SAli.Saidi@ARM.com /** start the dmas off after power is enabled */ 3157950SAli.Saidi@ARM.com void startDma(); 3167950SAli.Saidi@ARM.com 3177753SWilliam.Wang@arm.com /** DMA done event */ 3187753SWilliam.Wang@arm.com void dmaDone(); 3197753SWilliam.Wang@arm.com 3207753SWilliam.Wang@arm.com /** DMA framebuffer read event */ 3217753SWilliam.Wang@arm.com EventWrapper<Pl111, &Pl111::readFramebuffer> readEvent; 3227753SWilliam.Wang@arm.com 3237753SWilliam.Wang@arm.com /** Fill fifo */ 3247753SWilliam.Wang@arm.com EventWrapper<Pl111, &Pl111::fillFifo> fillFifoEvent; 3257753SWilliam.Wang@arm.com 3269395SAndreas.Sandberg@ARM.com /**@{*/ 3279395SAndreas.Sandberg@ARM.com /** 3289395SAndreas.Sandberg@ARM.com * All pre-allocated DMA done events 3299395SAndreas.Sandberg@ARM.com * 3309395SAndreas.Sandberg@ARM.com * The PL111 model preallocates maxOutstandingDma number of 3319395SAndreas.Sandberg@ARM.com * DmaDoneEvents to avoid having to heap allocate every single 3329395SAndreas.Sandberg@ARM.com * event when it is needed. In order to keep track of which events 3339395SAndreas.Sandberg@ARM.com * are in flight and which are ready to be used, we use two 3349395SAndreas.Sandberg@ARM.com * different vectors. dmaDoneEventAll contains <i>all</i> 3359395SAndreas.Sandberg@ARM.com * DmaDoneEvents that the object may use, while dmaDoneEventFree 3369395SAndreas.Sandberg@ARM.com * contains a list of currently <i>unused</i> events. When an 3379395SAndreas.Sandberg@ARM.com * event needs to be scheduled, the last element of the 3389395SAndreas.Sandberg@ARM.com * dmaDoneEventFree is used and removed from the list. When an 3399395SAndreas.Sandberg@ARM.com * event fires, it is added to the end of the 3409395SAndreas.Sandberg@ARM.com * dmaEventFreeList. dmaDoneEventAll is never used except for in 3419395SAndreas.Sandberg@ARM.com * initialization and serialization. 3429395SAndreas.Sandberg@ARM.com */ 3439395SAndreas.Sandberg@ARM.com std::vector<DmaDoneEvent> dmaDoneEventAll; 3449395SAndreas.Sandberg@ARM.com 3459395SAndreas.Sandberg@ARM.com /** Unused DMA done events that are ready to be scheduled */ 3469395SAndreas.Sandberg@ARM.com std::vector<DmaDoneEvent *> dmaDoneEventFree; 3479395SAndreas.Sandberg@ARM.com /**@}*/ 3487753SWilliam.Wang@arm.com 3497950SAli.Saidi@ARM.com /** Wrapper to create an event out of the interrupt */ 3507753SWilliam.Wang@arm.com EventWrapper<Pl111, &Pl111::generateInterrupt> intEvent; 3517753SWilliam.Wang@arm.com 3527753SWilliam.Wang@arm.com public: 3537753SWilliam.Wang@arm.com typedef Pl111Params Params; 3547753SWilliam.Wang@arm.com 3557753SWilliam.Wang@arm.com const Params * 3567753SWilliam.Wang@arm.com params() const 3577753SWilliam.Wang@arm.com { 3587753SWilliam.Wang@arm.com return dynamic_cast<const Params *>(_params); 3597753SWilliam.Wang@arm.com } 3607753SWilliam.Wang@arm.com Pl111(const Params *p); 3619086Sandreas.hansson@arm.com ~Pl111(); 3627753SWilliam.Wang@arm.com 3637753SWilliam.Wang@arm.com virtual Tick read(PacketPtr pkt); 3647753SWilliam.Wang@arm.com virtual Tick write(PacketPtr pkt); 3657753SWilliam.Wang@arm.com 3667753SWilliam.Wang@arm.com virtual void serialize(std::ostream &os); 3677753SWilliam.Wang@arm.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 3687753SWilliam.Wang@arm.com 3698711Sandreas.hansson@arm.com /** 3708711Sandreas.hansson@arm.com * Determine the address ranges that this device responds to. 3718711Sandreas.hansson@arm.com * 3728711Sandreas.hansson@arm.com * @return a list of non-overlapping address ranges 3737753SWilliam.Wang@arm.com */ 3749090Sandreas.hansson@arm.com AddrRangeList getAddrRanges() const; 3757753SWilliam.Wang@arm.com}; 3767753SWilliam.Wang@arm.com 3777753SWilliam.Wang@arm.com#endif 378