pl011.cc revision 7584:28ddf6d9e982
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 */ 42 43#include "base/trace.hh" 44#include "dev/arm/gic.hh" 45#include "dev/arm/pl011.hh" 46#include "dev/terminal.hh" 47#include "mem/packet.hh" 48#include "mem/packet_access.hh" 49#include "sim/sim_exit.hh" 50 51Pl011::Pl011(const Params *p) 52 : Uart(p), control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12), imsc(0), 53 rawInt(0), maskInt(0), intNum(p->int_num), gic(p->gic), 54 endOnEOT(p->end_on_eot), intDelay(p->int_delay), intEvent(this) 55{ 56 pioSize = 0xfff; 57} 58 59Tick 60Pl011::read(PacketPtr pkt) 61{ 62 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 63 64 Addr daddr = pkt->getAddr() - pioAddr; 65 pkt->allocate(); 66 67 DPRINTF(Uart, " read register %#x size=%d\n", daddr, pkt->getSize()); 68 69 // use a temporary data since the uart registers are read/written with 70 // different size operations 71 // 72 uint32_t data = 0; 73 74 switch(daddr) { 75 case UART_DR: 76 data = 0; 77 if (term->dataAvailable()) 78 data = term->in(); 79 break; 80 case UART_FR: 81 // For now we're infintely fast, so TX is never full, always empty, 82 // always clear to send 83 data = UART_FR_TXFE | UART_FR_CTS; 84 if (!term->dataAvailable()) 85 data |= UART_FR_RXFE; 86 DPRINTF(Uart, "Reading FR register as %#x rawInt=0x%x imsc=0x%x maskInt=0x%x\n", 87 data, rawInt, imsc, maskInt); 88 break; 89 case UART_CR: 90 data = control; 91 break; 92 case UART_IBRD: 93 data = ibrd; 94 break; 95 case UART_FBRD: 96 data = fbrd; 97 break; 98 case UART_LCRH: 99 data = lcrh; 100 break; 101 case UART_IFLS: 102 data = ifls; 103 break; 104 case UART_IMSC: 105 data = imsc; 106 break; 107 case UART_RIS: 108 data = rawInt; 109 DPRINTF(Uart, "Reading Raw Int status as 0x%x\n", rawInt); 110 break; 111 case UART_MIS: 112 DPRINTF(Uart, "Reading Masked Int status as 0x%x\n", rawInt); 113 data = maskInt; 114 break; 115 default: 116 if (daddr >= UART_PER_ID0 && daddr <= UART_CEL_ID3) { 117 // AMBA ID information 118 int byte; 119 byte = (daddr - UART_PER_ID0) << 1; 120 DPRINTF(AMBA, "--daddr=%#x shift=%d val=%#x\n", daddr, byte, 121 (ULL(0xb105f00d00341011) >> byte) & 0xFF); 122 data = (ULL(0xb105f00d00341011) >> byte) & 0xFF; 123 break; 124 } 125 panic("Tried to read PL011 at offset %#x that doesn't exist\n", daddr); 126 break; 127 } 128 129 switch(pkt->getSize()) { 130 case 1: 131 pkt->set<uint8_t>(data); 132 break; 133 case 2: 134 pkt->set<uint16_t>(data); 135 break; 136 case 4: 137 pkt->set<uint32_t>(data); 138 break; 139 default: 140 panic("Uart read size too big?\n"); 141 break; 142 } 143 144 145 pkt->makeAtomicResponse(); 146 return pioDelay; 147} 148 149Tick 150Pl011::write(PacketPtr pkt) 151{ 152 153 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 154 155 Addr daddr = pkt->getAddr() - pioAddr; 156 157 DPRINTF(Uart, " write register %#x value %#x size=%d\n", daddr, 158 pkt->get<uint8_t>(), pkt->getSize()); 159 160 // use a temporary data since the uart registers are read/written with 161 // different size operations 162 // 163 uint32_t data = 0; 164 165 switch(pkt->getSize()) { 166 case 1: 167 data = pkt->get<uint8_t>(); 168 break; 169 case 2: 170 data = pkt->get<uint16_t>(); 171 break; 172 case 4: 173 data = pkt->get<uint32_t>(); 174 break; 175 default: 176 panic("Uart write size too big?\n"); 177 break; 178 } 179 180 181 switch (daddr) { 182 case UART_DR: 183 if ((data & 0xFF) == 0x04 && endOnEOT) 184 exitSimLoop("UART received EOT", 0); 185 186 term->out(data & 0xFF); 187 188 if (imsc.txim) { 189 DPRINTF(Uart, "TX int enabled, scheduling interruptt\n"); 190 rawInt.txim = 1; 191 if (!intEvent.scheduled()) 192 schedule(intEvent, curTick + intDelay); 193 } 194 195 break; 196 case UART_CR: 197 control = data; 198 break; 199 case UART_IBRD: 200 ibrd = data; 201 break; 202 case UART_FBRD: 203 fbrd = data; 204 break; 205 case UART_LCRH: 206 lcrh = data; 207 break; 208 case UART_IFLS: 209 ifls = data; 210 break; 211 case UART_IMSC: 212 imsc = data; 213 214 if (imsc.rimim || imsc.ctsmim || imsc.dcdmim || imsc.dsrmim 215 || imsc.feim || imsc.peim || imsc.beim || imsc.oeim || imsc.rsvd) 216 panic("Unknown interrupt enabled\n"); 217 218 if (imsc.txim) { 219 DPRINTF(Uart, "Writing to IMSC: TX int enabled, scheduling interruptt\n"); 220 rawInt.txim = 1; 221 if (!intEvent.scheduled()) 222 schedule(intEvent, curTick + intDelay); 223 } 224 225 break; 226 227 case UART_ICR: 228 DPRINTF(Uart, "Clearing interrupts 0x%x\n", data); 229 rawInt = rawInt & ~data; 230 maskInt = rawInt & imsc; 231 232 DPRINTF(Uart, " -- Masked interrupts 0x%x\n", maskInt); 233 234 if (!maskInt) 235 gic->clearInt(intNum); 236 237 break; 238 default: 239 panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr); 240 break; 241 } 242 pkt->makeAtomicResponse(); 243 return pioDelay; 244} 245 246void 247Pl011::dataAvailable() 248{ 249 /*@todo ignore the fifo, just say we have data now 250 * We might want to fix this, or we might not care */ 251 rawInt.rxim = 1; 252 rawInt.rtim = 1; 253 254 DPRINTF(Uart, "Data available, scheduling interrupt\n"); 255 256 if (!intEvent.scheduled()) 257 schedule(intEvent, curTick + intDelay); 258} 259 260void 261Pl011::generateInterrupt() 262{ 263 DPRINTF(Uart, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n", 264 imsc, rawInt, maskInt); 265 maskInt = imsc & rawInt; 266 267 if (maskInt.rxim || maskInt.rtim || maskInt.txim) { 268 gic->sendInt(intNum); 269 DPRINTF(Uart, " -- Generated\n"); 270 } 271 272} 273 274 275 276void 277Pl011::serialize(std::ostream &os) 278{ 279 panic("Need to implement serialization\n"); 280} 281 282void 283Pl011::unserialize(Checkpoint *cp, const std::string §ion) 284{ 285 panic("Need to implement serialization\n"); 286} 287 288Pl011 * 289Pl011Params::create() 290{ 291 return new Pl011(this); 292} 293