pl011.cc revision 7584:28ddf6d9e982
16019SN/A/* 26019SN/A * Copyright (c) 2010 ARM Limited 36019SN/A * All rights reserved 46019SN/A * 56019SN/A * The license below extends only to copyright in the software and shall 66019SN/A * not be construed as granting a license to any other intellectual 76019SN/A * property including but not limited to intellectual property relating 86019SN/A * to a hardware implementation of the functionality of the software 96019SN/A * licensed hereunder. You may use the software subject to the license 106019SN/A * terms below provided that you ensure that this notice is replicated 116019SN/A * unmodified and in its entirety in all distributions of the software, 126019SN/A * modified or unmodified, in source code or in binary form. 136019SN/A * 146019SN/A * Copyright (c) 2005 The Regents of The University of Michigan 156019SN/A * All rights reserved. 166019SN/A * 176019SN/A * Redistribution and use in source and binary forms, with or without 186019SN/A * modification, are permitted provided that the following conditions are 196019SN/A * met: redistributions of source code must retain the above copyright 206019SN/A * notice, this list of conditions and the following disclaimer; 216019SN/A * redistributions in binary form must reproduce the above copyright 226019SN/A * notice, this list of conditions and the following disclaimer in the 236019SN/A * documentation and/or other materials provided with the distribution; 246019SN/A * neither the name of the copyright holders nor the names of its 256019SN/A * contributors may be used to endorse or promote products derived from 266019SN/A * this software without specific prior written permission. 276019SN/A * 286019SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019SN/A * 406019SN/A * Authors: Ali Saidi 416019SN/A */ 426019SN/A 436019SN/A#include "base/trace.hh" 446019SN/A#include "dev/arm/gic.hh" 456250SN/A#include "dev/arm/pl011.hh" 466019SN/A#include "dev/terminal.hh" 476019SN/A#include "mem/packet.hh" 486019SN/A#include "mem/packet_access.hh" 496019SN/A#include "sim/sim_exit.hh" 506019SN/A 516019SN/APl011::Pl011(const Params *p) 528737Skoansin.tan@gmail.com : Uart(p), control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12), imsc(0), 536019SN/A rawInt(0), maskInt(0), intNum(p->int_num), gic(p->gic), 546019SN/A endOnEOT(p->end_on_eot), intDelay(p->int_delay), intEvent(this) 557848SAli.Saidi@ARM.com{ 567848SAli.Saidi@ARM.com pioSize = 0xfff; 577848SAli.Saidi@ARM.com} 587848SAli.Saidi@ARM.com 597848SAli.Saidi@ARM.comTick 606019SN/APl011::read(PacketPtr pkt) 616019SN/A{ 626019SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 636019SN/A 646019SN/A Addr daddr = pkt->getAddr() - pioAddr; 656019SN/A pkt->allocate(); 666019SN/A 676019SN/A DPRINTF(Uart, " read register %#x size=%d\n", daddr, pkt->getSize()); 686019SN/A 696019SN/A // use a temporary data since the uart registers are read/written with 706019SN/A // different size operations 716019SN/A // 726019SN/A uint32_t data = 0; 736019SN/A 746019SN/A switch(daddr) { 756019SN/A case UART_DR: 766019SN/A data = 0; 776019SN/A if (term->dataAvailable()) 786019SN/A data = term->in(); 796019SN/A break; 806019SN/A case UART_FR: 816019SN/A // For now we're infintely fast, so TX is never full, always empty, 826019SN/A // always clear to send 836019SN/A data = UART_FR_TXFE | UART_FR_CTS; 846019SN/A if (!term->dataAvailable()) 856019SN/A data |= UART_FR_RXFE; 866019SN/A DPRINTF(Uart, "Reading FR register as %#x rawInt=0x%x imsc=0x%x maskInt=0x%x\n", 876019SN/A data, rawInt, imsc, maskInt); 886019SN/A break; 896019SN/A case UART_CR: 906019SN/A data = control; 916019SN/A break; 926019SN/A case UART_IBRD: 936019SN/A data = ibrd; 946019SN/A break; 956019SN/A case UART_FBRD: 966019SN/A data = fbrd; 977168SAli.Saidi@ARM.com break; 987168SAli.Saidi@ARM.com case UART_LCRH: 996019SN/A data = lcrh; 1006019SN/A break; 101 case UART_IFLS: 102 data = ifls; 103 break; 104 case UART_IMSC: 105 data = imsc; 106 break; 107 case UART_RIS: 108 data = rawInt; 109 DPRINTF(Uart, "Reading Raw Int status as 0x%x\n", rawInt); 110 break; 111 case UART_MIS: 112 DPRINTF(Uart, "Reading Masked Int status as 0x%x\n", rawInt); 113 data = maskInt; 114 break; 115 default: 116 if (daddr >= UART_PER_ID0 && daddr <= UART_CEL_ID3) { 117 // AMBA ID information 118 int byte; 119 byte = (daddr - UART_PER_ID0) << 1; 120 DPRINTF(AMBA, "--daddr=%#x shift=%d val=%#x\n", daddr, byte, 121 (ULL(0xb105f00d00341011) >> byte) & 0xFF); 122 data = (ULL(0xb105f00d00341011) >> byte) & 0xFF; 123 break; 124 } 125 panic("Tried to read PL011 at offset %#x that doesn't exist\n", daddr); 126 break; 127 } 128 129 switch(pkt->getSize()) { 130 case 1: 131 pkt->set<uint8_t>(data); 132 break; 133 case 2: 134 pkt->set<uint16_t>(data); 135 break; 136 case 4: 137 pkt->set<uint32_t>(data); 138 break; 139 default: 140 panic("Uart read size too big?\n"); 141 break; 142 } 143 144 145 pkt->makeAtomicResponse(); 146 return pioDelay; 147} 148 149Tick 150Pl011::write(PacketPtr pkt) 151{ 152 153 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 154 155 Addr daddr = pkt->getAddr() - pioAddr; 156 157 DPRINTF(Uart, " write register %#x value %#x size=%d\n", daddr, 158 pkt->get<uint8_t>(), pkt->getSize()); 159 160 // use a temporary data since the uart registers are read/written with 161 // different size operations 162 // 163 uint32_t data = 0; 164 165 switch(pkt->getSize()) { 166 case 1: 167 data = pkt->get<uint8_t>(); 168 break; 169 case 2: 170 data = pkt->get<uint16_t>(); 171 break; 172 case 4: 173 data = pkt->get<uint32_t>(); 174 break; 175 default: 176 panic("Uart write size too big?\n"); 177 break; 178 } 179 180 181 switch (daddr) { 182 case UART_DR: 183 if ((data & 0xFF) == 0x04 && endOnEOT) 184 exitSimLoop("UART received EOT", 0); 185 186 term->out(data & 0xFF); 187 188 if (imsc.txim) { 189 DPRINTF(Uart, "TX int enabled, scheduling interruptt\n"); 190 rawInt.txim = 1; 191 if (!intEvent.scheduled()) 192 schedule(intEvent, curTick + intDelay); 193 } 194 195 break; 196 case UART_CR: 197 control = data; 198 break; 199 case UART_IBRD: 200 ibrd = data; 201 break; 202 case UART_FBRD: 203 fbrd = data; 204 break; 205 case UART_LCRH: 206 lcrh = data; 207 break; 208 case UART_IFLS: 209 ifls = data; 210 break; 211 case UART_IMSC: 212 imsc = data; 213 214 if (imsc.rimim || imsc.ctsmim || imsc.dcdmim || imsc.dsrmim 215 || imsc.feim || imsc.peim || imsc.beim || imsc.oeim || imsc.rsvd) 216 panic("Unknown interrupt enabled\n"); 217 218 if (imsc.txim) { 219 DPRINTF(Uart, "Writing to IMSC: TX int enabled, scheduling interruptt\n"); 220 rawInt.txim = 1; 221 if (!intEvent.scheduled()) 222 schedule(intEvent, curTick + intDelay); 223 } 224 225 break; 226 227 case UART_ICR: 228 DPRINTF(Uart, "Clearing interrupts 0x%x\n", data); 229 rawInt = rawInt & ~data; 230 maskInt = rawInt & imsc; 231 232 DPRINTF(Uart, " -- Masked interrupts 0x%x\n", maskInt); 233 234 if (!maskInt) 235 gic->clearInt(intNum); 236 237 break; 238 default: 239 panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr); 240 break; 241 } 242 pkt->makeAtomicResponse(); 243 return pioDelay; 244} 245 246void 247Pl011::dataAvailable() 248{ 249 /*@todo ignore the fifo, just say we have data now 250 * We might want to fix this, or we might not care */ 251 rawInt.rxim = 1; 252 rawInt.rtim = 1; 253 254 DPRINTF(Uart, "Data available, scheduling interrupt\n"); 255 256 if (!intEvent.scheduled()) 257 schedule(intEvent, curTick + intDelay); 258} 259 260void 261Pl011::generateInterrupt() 262{ 263 DPRINTF(Uart, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n", 264 imsc, rawInt, maskInt); 265 maskInt = imsc & rawInt; 266 267 if (maskInt.rxim || maskInt.rtim || maskInt.txim) { 268 gic->sendInt(intNum); 269 DPRINTF(Uart, " -- Generated\n"); 270 } 271 272} 273 274 275 276void 277Pl011::serialize(std::ostream &os) 278{ 279 panic("Need to implement serialization\n"); 280} 281 282void 283Pl011::unserialize(Checkpoint *cp, const std::string §ion) 284{ 285 panic("Need to implement serialization\n"); 286} 287 288Pl011 * 289Pl011Params::create() 290{ 291 return new Pl011(this); 292} 293