pl011.cc revision 9525
17584SAli.Saidi@arm.com/* 27584SAli.Saidi@arm.com * Copyright (c) 2010 ARM Limited 37584SAli.Saidi@arm.com * All rights reserved 47584SAli.Saidi@arm.com * 57584SAli.Saidi@arm.com * The license below extends only to copyright in the software and shall 67584SAli.Saidi@arm.com * not be construed as granting a license to any other intellectual 77584SAli.Saidi@arm.com * property including but not limited to intellectual property relating 87584SAli.Saidi@arm.com * to a hardware implementation of the functionality of the software 97584SAli.Saidi@arm.com * licensed hereunder. You may use the software subject to the license 107584SAli.Saidi@arm.com * terms below provided that you ensure that this notice is replicated 117584SAli.Saidi@arm.com * unmodified and in its entirety in all distributions of the software, 127584SAli.Saidi@arm.com * modified or unmodified, in source code or in binary form. 137584SAli.Saidi@arm.com * 147584SAli.Saidi@arm.com * Copyright (c) 2005 The Regents of The University of Michigan 157584SAli.Saidi@arm.com * All rights reserved. 167584SAli.Saidi@arm.com * 177584SAli.Saidi@arm.com * Redistribution and use in source and binary forms, with or without 187584SAli.Saidi@arm.com * modification, are permitted provided that the following conditions are 197584SAli.Saidi@arm.com * met: redistributions of source code must retain the above copyright 207584SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer; 217584SAli.Saidi@arm.com * redistributions in binary form must reproduce the above copyright 227584SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer in the 237584SAli.Saidi@arm.com * documentation and/or other materials provided with the distribution; 247584SAli.Saidi@arm.com * neither the name of the copyright holders nor the names of its 257584SAli.Saidi@arm.com * contributors may be used to endorse or promote products derived from 267584SAli.Saidi@arm.com * this software without specific prior written permission. 277584SAli.Saidi@arm.com * 287584SAli.Saidi@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297584SAli.Saidi@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307584SAli.Saidi@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317584SAli.Saidi@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327584SAli.Saidi@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337584SAli.Saidi@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347584SAli.Saidi@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357584SAli.Saidi@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367584SAli.Saidi@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377584SAli.Saidi@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387584SAli.Saidi@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397584SAli.Saidi@arm.com * 407584SAli.Saidi@arm.com * Authors: Ali Saidi 417584SAli.Saidi@arm.com */ 427584SAli.Saidi@arm.com 437584SAli.Saidi@arm.com#include "base/trace.hh" 448245Snate@binkert.org#include "debug/Checkpoint.hh" 458245Snate@binkert.org#include "debug/Uart.hh" 467587SAli.Saidi@arm.com#include "dev/arm/amba_device.hh" 479525SAndreas.Sandberg@ARM.com#include "dev/arm/base_gic.hh" 487584SAli.Saidi@arm.com#include "dev/arm/pl011.hh" 497584SAli.Saidi@arm.com#include "dev/terminal.hh" 507584SAli.Saidi@arm.com#include "mem/packet.hh" 517584SAli.Saidi@arm.com#include "mem/packet_access.hh" 527584SAli.Saidi@arm.com#include "sim/sim_exit.hh" 537584SAli.Saidi@arm.com 547584SAli.Saidi@arm.comPl011::Pl011(const Params *p) 557584SAli.Saidi@arm.com : Uart(p), control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12), imsc(0), 567584SAli.Saidi@arm.com rawInt(0), maskInt(0), intNum(p->int_num), gic(p->gic), 577584SAli.Saidi@arm.com endOnEOT(p->end_on_eot), intDelay(p->int_delay), intEvent(this) 587584SAli.Saidi@arm.com{ 597584SAli.Saidi@arm.com pioSize = 0xfff; 607584SAli.Saidi@arm.com} 617584SAli.Saidi@arm.com 627584SAli.Saidi@arm.comTick 637584SAli.Saidi@arm.comPl011::read(PacketPtr pkt) 647584SAli.Saidi@arm.com{ 657584SAli.Saidi@arm.com assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 667584SAli.Saidi@arm.com 677584SAli.Saidi@arm.com Addr daddr = pkt->getAddr() - pioAddr; 687584SAli.Saidi@arm.com pkt->allocate(); 697584SAli.Saidi@arm.com 707584SAli.Saidi@arm.com DPRINTF(Uart, " read register %#x size=%d\n", daddr, pkt->getSize()); 717584SAli.Saidi@arm.com 727584SAli.Saidi@arm.com // use a temporary data since the uart registers are read/written with 737584SAli.Saidi@arm.com // different size operations 747584SAli.Saidi@arm.com // 757584SAli.Saidi@arm.com uint32_t data = 0; 767584SAli.Saidi@arm.com 777584SAli.Saidi@arm.com switch(daddr) { 787584SAli.Saidi@arm.com case UART_DR: 797584SAli.Saidi@arm.com data = 0; 807584SAli.Saidi@arm.com if (term->dataAvailable()) 817584SAli.Saidi@arm.com data = term->in(); 827584SAli.Saidi@arm.com break; 837584SAli.Saidi@arm.com case UART_FR: 847584SAli.Saidi@arm.com // For now we're infintely fast, so TX is never full, always empty, 857584SAli.Saidi@arm.com // always clear to send 867584SAli.Saidi@arm.com data = UART_FR_TXFE | UART_FR_CTS; 877584SAli.Saidi@arm.com if (!term->dataAvailable()) 887584SAli.Saidi@arm.com data |= UART_FR_RXFE; 897584SAli.Saidi@arm.com DPRINTF(Uart, "Reading FR register as %#x rawInt=0x%x imsc=0x%x maskInt=0x%x\n", 907584SAli.Saidi@arm.com data, rawInt, imsc, maskInt); 917584SAli.Saidi@arm.com break; 927584SAli.Saidi@arm.com case UART_CR: 937584SAli.Saidi@arm.com data = control; 947584SAli.Saidi@arm.com break; 957584SAli.Saidi@arm.com case UART_IBRD: 967584SAli.Saidi@arm.com data = ibrd; 977584SAli.Saidi@arm.com break; 987584SAli.Saidi@arm.com case UART_FBRD: 997584SAli.Saidi@arm.com data = fbrd; 1007584SAli.Saidi@arm.com break; 1017584SAli.Saidi@arm.com case UART_LCRH: 1027584SAli.Saidi@arm.com data = lcrh; 1037584SAli.Saidi@arm.com break; 1047584SAli.Saidi@arm.com case UART_IFLS: 1057584SAli.Saidi@arm.com data = ifls; 1067584SAli.Saidi@arm.com break; 1077584SAli.Saidi@arm.com case UART_IMSC: 1087584SAli.Saidi@arm.com data = imsc; 1097584SAli.Saidi@arm.com break; 1107584SAli.Saidi@arm.com case UART_RIS: 1117584SAli.Saidi@arm.com data = rawInt; 1127584SAli.Saidi@arm.com DPRINTF(Uart, "Reading Raw Int status as 0x%x\n", rawInt); 1137584SAli.Saidi@arm.com break; 1147584SAli.Saidi@arm.com case UART_MIS: 1157584SAli.Saidi@arm.com DPRINTF(Uart, "Reading Masked Int status as 0x%x\n", rawInt); 1167584SAli.Saidi@arm.com data = maskInt; 1177584SAli.Saidi@arm.com break; 1187584SAli.Saidi@arm.com default: 1197587SAli.Saidi@arm.com if (AmbaDev::readId(pkt, AMBA_ID, pioAddr)) { 1207587SAli.Saidi@arm.com // Hack for variable size accesses 1217587SAli.Saidi@arm.com data = pkt->get<uint32_t>(); 1227584SAli.Saidi@arm.com break; 1237584SAli.Saidi@arm.com } 1247587SAli.Saidi@arm.com 1257584SAli.Saidi@arm.com panic("Tried to read PL011 at offset %#x that doesn't exist\n", daddr); 1267584SAli.Saidi@arm.com break; 1277584SAli.Saidi@arm.com } 1287584SAli.Saidi@arm.com 1297584SAli.Saidi@arm.com switch(pkt->getSize()) { 1307584SAli.Saidi@arm.com case 1: 1317584SAli.Saidi@arm.com pkt->set<uint8_t>(data); 1327584SAli.Saidi@arm.com break; 1337584SAli.Saidi@arm.com case 2: 1347584SAli.Saidi@arm.com pkt->set<uint16_t>(data); 1357584SAli.Saidi@arm.com break; 1367584SAli.Saidi@arm.com case 4: 1377584SAli.Saidi@arm.com pkt->set<uint32_t>(data); 1387584SAli.Saidi@arm.com break; 1397584SAli.Saidi@arm.com default: 1407584SAli.Saidi@arm.com panic("Uart read size too big?\n"); 1417584SAli.Saidi@arm.com break; 1427584SAli.Saidi@arm.com } 1437584SAli.Saidi@arm.com 1447584SAli.Saidi@arm.com 1457584SAli.Saidi@arm.com pkt->makeAtomicResponse(); 1467584SAli.Saidi@arm.com return pioDelay; 1477584SAli.Saidi@arm.com} 1487584SAli.Saidi@arm.com 1497584SAli.Saidi@arm.comTick 1507584SAli.Saidi@arm.comPl011::write(PacketPtr pkt) 1517584SAli.Saidi@arm.com{ 1527584SAli.Saidi@arm.com 1537584SAli.Saidi@arm.com assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1547584SAli.Saidi@arm.com 1557584SAli.Saidi@arm.com Addr daddr = pkt->getAddr() - pioAddr; 1567584SAli.Saidi@arm.com 1577584SAli.Saidi@arm.com DPRINTF(Uart, " write register %#x value %#x size=%d\n", daddr, 1587584SAli.Saidi@arm.com pkt->get<uint8_t>(), pkt->getSize()); 1597584SAli.Saidi@arm.com 1607584SAli.Saidi@arm.com // use a temporary data since the uart registers are read/written with 1617584SAli.Saidi@arm.com // different size operations 1627584SAli.Saidi@arm.com // 1637584SAli.Saidi@arm.com uint32_t data = 0; 1647584SAli.Saidi@arm.com 1657584SAli.Saidi@arm.com switch(pkt->getSize()) { 1667584SAli.Saidi@arm.com case 1: 1677584SAli.Saidi@arm.com data = pkt->get<uint8_t>(); 1687584SAli.Saidi@arm.com break; 1697584SAli.Saidi@arm.com case 2: 1707584SAli.Saidi@arm.com data = pkt->get<uint16_t>(); 1717584SAli.Saidi@arm.com break; 1727584SAli.Saidi@arm.com case 4: 1737584SAli.Saidi@arm.com data = pkt->get<uint32_t>(); 1747584SAli.Saidi@arm.com break; 1757584SAli.Saidi@arm.com default: 1767584SAli.Saidi@arm.com panic("Uart write size too big?\n"); 1777584SAli.Saidi@arm.com break; 1787584SAli.Saidi@arm.com } 1797584SAli.Saidi@arm.com 1807584SAli.Saidi@arm.com 1817584SAli.Saidi@arm.com switch (daddr) { 1827584SAli.Saidi@arm.com case UART_DR: 1837584SAli.Saidi@arm.com if ((data & 0xFF) == 0x04 && endOnEOT) 1847584SAli.Saidi@arm.com exitSimLoop("UART received EOT", 0); 1857584SAli.Saidi@arm.com 1867584SAli.Saidi@arm.com term->out(data & 0xFF); 1877584SAli.Saidi@arm.com 1889001Schander.sudanthi@arm.com //raw interrupt is set regardless of imsc.txim 1899001Schander.sudanthi@arm.com rawInt.txim = 1; 1907584SAli.Saidi@arm.com if (imsc.txim) { 1917584SAli.Saidi@arm.com DPRINTF(Uart, "TX int enabled, scheduling interruptt\n"); 1927584SAli.Saidi@arm.com if (!intEvent.scheduled()) 1937823Ssteve.reinhardt@amd.com schedule(intEvent, curTick() + intDelay); 1947584SAli.Saidi@arm.com } 1957584SAli.Saidi@arm.com 1967584SAli.Saidi@arm.com break; 1977584SAli.Saidi@arm.com case UART_CR: 1987584SAli.Saidi@arm.com control = data; 1997584SAli.Saidi@arm.com break; 2007584SAli.Saidi@arm.com case UART_IBRD: 2017584SAli.Saidi@arm.com ibrd = data; 2027584SAli.Saidi@arm.com break; 2037584SAli.Saidi@arm.com case UART_FBRD: 2047584SAli.Saidi@arm.com fbrd = data; 2057584SAli.Saidi@arm.com break; 2067584SAli.Saidi@arm.com case UART_LCRH: 2077584SAli.Saidi@arm.com lcrh = data; 2087584SAli.Saidi@arm.com break; 2097584SAli.Saidi@arm.com case UART_IFLS: 2107584SAli.Saidi@arm.com ifls = data; 2117584SAli.Saidi@arm.com break; 2127584SAli.Saidi@arm.com case UART_IMSC: 2137584SAli.Saidi@arm.com imsc = data; 2147584SAli.Saidi@arm.com 2157584SAli.Saidi@arm.com if (imsc.rimim || imsc.ctsmim || imsc.dcdmim || imsc.dsrmim 2167584SAli.Saidi@arm.com || imsc.feim || imsc.peim || imsc.beim || imsc.oeim || imsc.rsvd) 2177584SAli.Saidi@arm.com panic("Unknown interrupt enabled\n"); 2187584SAli.Saidi@arm.com 2197584SAli.Saidi@arm.com if (imsc.txim) { 2207584SAli.Saidi@arm.com DPRINTF(Uart, "Writing to IMSC: TX int enabled, scheduling interruptt\n"); 2217584SAli.Saidi@arm.com rawInt.txim = 1; 2227584SAli.Saidi@arm.com if (!intEvent.scheduled()) 2237823Ssteve.reinhardt@amd.com schedule(intEvent, curTick() + intDelay); 2247584SAli.Saidi@arm.com } 2257584SAli.Saidi@arm.com 2267584SAli.Saidi@arm.com break; 2277584SAli.Saidi@arm.com 2287584SAli.Saidi@arm.com case UART_ICR: 2297584SAli.Saidi@arm.com DPRINTF(Uart, "Clearing interrupts 0x%x\n", data); 2307584SAli.Saidi@arm.com rawInt = rawInt & ~data; 2317584SAli.Saidi@arm.com maskInt = rawInt & imsc; 2327584SAli.Saidi@arm.com 2337584SAli.Saidi@arm.com DPRINTF(Uart, " -- Masked interrupts 0x%x\n", maskInt); 2347584SAli.Saidi@arm.com 2357584SAli.Saidi@arm.com if (!maskInt) 2367584SAli.Saidi@arm.com gic->clearInt(intNum); 2377584SAli.Saidi@arm.com 2387584SAli.Saidi@arm.com break; 2397584SAli.Saidi@arm.com default: 2407584SAli.Saidi@arm.com panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr); 2417584SAli.Saidi@arm.com break; 2427584SAli.Saidi@arm.com } 2437584SAli.Saidi@arm.com pkt->makeAtomicResponse(); 2447584SAli.Saidi@arm.com return pioDelay; 2457584SAli.Saidi@arm.com} 2467584SAli.Saidi@arm.com 2477584SAli.Saidi@arm.comvoid 2487584SAli.Saidi@arm.comPl011::dataAvailable() 2497584SAli.Saidi@arm.com{ 2507584SAli.Saidi@arm.com /*@todo ignore the fifo, just say we have data now 2517584SAli.Saidi@arm.com * We might want to fix this, or we might not care */ 2527584SAli.Saidi@arm.com rawInt.rxim = 1; 2537584SAli.Saidi@arm.com rawInt.rtim = 1; 2547584SAli.Saidi@arm.com 2557584SAli.Saidi@arm.com DPRINTF(Uart, "Data available, scheduling interrupt\n"); 2567584SAli.Saidi@arm.com 2577584SAli.Saidi@arm.com if (!intEvent.scheduled()) 2587823Ssteve.reinhardt@amd.com schedule(intEvent, curTick() + intDelay); 2597584SAli.Saidi@arm.com} 2607584SAli.Saidi@arm.com 2617584SAli.Saidi@arm.comvoid 2627584SAli.Saidi@arm.comPl011::generateInterrupt() 2637584SAli.Saidi@arm.com{ 2647584SAli.Saidi@arm.com DPRINTF(Uart, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n", 2657584SAli.Saidi@arm.com imsc, rawInt, maskInt); 2667584SAli.Saidi@arm.com maskInt = imsc & rawInt; 2677584SAli.Saidi@arm.com 2687584SAli.Saidi@arm.com if (maskInt.rxim || maskInt.rtim || maskInt.txim) { 2697584SAli.Saidi@arm.com gic->sendInt(intNum); 2707584SAli.Saidi@arm.com DPRINTF(Uart, " -- Generated\n"); 2717584SAli.Saidi@arm.com } 2727584SAli.Saidi@arm.com 2737584SAli.Saidi@arm.com} 2747584SAli.Saidi@arm.com 2757584SAli.Saidi@arm.com 2767584SAli.Saidi@arm.com 2777584SAli.Saidi@arm.comvoid 2787584SAli.Saidi@arm.comPl011::serialize(std::ostream &os) 2797584SAli.Saidi@arm.com{ 2807733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Serializing Arm PL011\n"); 2817733SAli.Saidi@ARM.com SERIALIZE_SCALAR(control); 2827733SAli.Saidi@ARM.com SERIALIZE_SCALAR(fbrd); 2837733SAli.Saidi@ARM.com SERIALIZE_SCALAR(ibrd); 2847733SAli.Saidi@ARM.com SERIALIZE_SCALAR(lcrh); 2857733SAli.Saidi@ARM.com SERIALIZE_SCALAR(ifls); 2867733SAli.Saidi@ARM.com 2877733SAli.Saidi@ARM.com uint16_t imsc_serial = imsc; 2887733SAli.Saidi@ARM.com SERIALIZE_SCALAR(imsc_serial); 2897733SAli.Saidi@ARM.com 2907733SAli.Saidi@ARM.com uint16_t rawInt_serial = rawInt; 2917733SAli.Saidi@ARM.com SERIALIZE_SCALAR(rawInt_serial); 2927733SAli.Saidi@ARM.com 2937733SAli.Saidi@ARM.com uint16_t maskInt_serial = maskInt; 2947733SAli.Saidi@ARM.com SERIALIZE_SCALAR(maskInt_serial); 2957733SAli.Saidi@ARM.com 2967733SAli.Saidi@ARM.com SERIALIZE_SCALAR(endOnEOT); 2977733SAli.Saidi@ARM.com SERIALIZE_SCALAR(intDelay); 2987584SAli.Saidi@arm.com} 2997584SAli.Saidi@arm.com 3007584SAli.Saidi@arm.comvoid 3017584SAli.Saidi@arm.comPl011::unserialize(Checkpoint *cp, const std::string §ion) 3027584SAli.Saidi@arm.com{ 3037733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Unserializing Arm PL011\n"); 3047733SAli.Saidi@ARM.com 3057733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(control); 3067733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(fbrd); 3077733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(ibrd); 3087733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(lcrh); 3097733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(ifls); 3107733SAli.Saidi@ARM.com 3117733SAli.Saidi@ARM.com uint16_t imsc_serial; 3127733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(imsc_serial); 3137733SAli.Saidi@ARM.com imsc = imsc_serial; 3147733SAli.Saidi@ARM.com 3157733SAli.Saidi@ARM.com uint16_t rawInt_serial; 3167733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(rawInt_serial); 3177733SAli.Saidi@ARM.com rawInt = rawInt_serial; 3187733SAli.Saidi@ARM.com 3197733SAli.Saidi@ARM.com uint16_t maskInt_serial; 3207733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(maskInt_serial); 3217733SAli.Saidi@ARM.com maskInt = maskInt_serial; 3227733SAli.Saidi@ARM.com 3237733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(endOnEOT); 3247733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(intDelay); 3257584SAli.Saidi@arm.com} 3267584SAli.Saidi@arm.com 3277584SAli.Saidi@arm.comPl011 * 3287584SAli.Saidi@arm.comPl011Params::create() 3297584SAli.Saidi@arm.com{ 3307584SAli.Saidi@arm.com return new Pl011(this); 3317584SAli.Saidi@arm.com} 332