gic_v3_redistributor.cc revision 13921
113531Sjairo.balart@metempsy.com/* 213531Sjairo.balart@metempsy.com * Copyright (c) 2018 Metempsy Technology Consulting 313531Sjairo.balart@metempsy.com * All rights reserved. 413531Sjairo.balart@metempsy.com * 513531Sjairo.balart@metempsy.com * Redistribution and use in source and binary forms, with or without 613531Sjairo.balart@metempsy.com * modification, are permitted provided that the following conditions are 713531Sjairo.balart@metempsy.com * met: redistributions of source code must retain the above copyright 813531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer; 913531Sjairo.balart@metempsy.com * redistributions in binary form must reproduce the above copyright 1013531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer in the 1113531Sjairo.balart@metempsy.com * documentation and/or other materials provided with the distribution; 1213531Sjairo.balart@metempsy.com * neither the name of the copyright holders nor the names of its 1313531Sjairo.balart@metempsy.com * contributors may be used to endorse or promote products derived from 1413531Sjairo.balart@metempsy.com * this software without specific prior written permission. 1513531Sjairo.balart@metempsy.com * 1613531Sjairo.balart@metempsy.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1713531Sjairo.balart@metempsy.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1813531Sjairo.balart@metempsy.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1913531Sjairo.balart@metempsy.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2013531Sjairo.balart@metempsy.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2113531Sjairo.balart@metempsy.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2213531Sjairo.balart@metempsy.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2313531Sjairo.balart@metempsy.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2413531Sjairo.balart@metempsy.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2513531Sjairo.balart@metempsy.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2613531Sjairo.balart@metempsy.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2713531Sjairo.balart@metempsy.com * 2813531Sjairo.balart@metempsy.com * Authors: Jairo Balart 2913531Sjairo.balart@metempsy.com */ 3013531Sjairo.balart@metempsy.com 3113531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_redistributor.hh" 3213531Sjairo.balart@metempsy.com 3313531Sjairo.balart@metempsy.com#include "arch/arm/utility.hh" 3413531Sjairo.balart@metempsy.com#include "debug/GIC.hh" 3513531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_cpu_interface.hh" 3613531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_distributor.hh" 3713690Sjairo.balart@metempsy.com#include "mem/fs_translating_port_proxy.hh" 3813531Sjairo.balart@metempsy.com 3913531Sjairo.balart@metempsy.comconst AddrRange Gicv3Redistributor::GICR_IPRIORITYR(SGI_base + 0x0400, 4013756Sjairo.balart@metempsy.com SGI_base + 0x041f); 4113531Sjairo.balart@metempsy.com 4213531Sjairo.balart@metempsy.comGicv3Redistributor::Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id) 4313531Sjairo.balart@metempsy.com : gic(gic), 4413531Sjairo.balart@metempsy.com distributor(nullptr), 4513531Sjairo.balart@metempsy.com cpuInterface(nullptr), 4613531Sjairo.balart@metempsy.com cpuId(cpu_id), 4713531Sjairo.balart@metempsy.com irqGroup(Gicv3::SGI_MAX + Gicv3::PPI_MAX), 4813531Sjairo.balart@metempsy.com irqEnabled(Gicv3::SGI_MAX + Gicv3::PPI_MAX), 4913531Sjairo.balart@metempsy.com irqPending(Gicv3::SGI_MAX + Gicv3::PPI_MAX), 5013531Sjairo.balart@metempsy.com irqActive(Gicv3::SGI_MAX + Gicv3::PPI_MAX), 5113531Sjairo.balart@metempsy.com irqPriority(Gicv3::SGI_MAX + Gicv3::PPI_MAX), 5213531Sjairo.balart@metempsy.com irqConfig(Gicv3::SGI_MAX + Gicv3::PPI_MAX), 5313531Sjairo.balart@metempsy.com irqGrpmod(Gicv3::SGI_MAX + Gicv3::PPI_MAX), 5413878Sgiacomo.travaglini@arm.com irqNsacr(Gicv3::SGI_MAX + Gicv3::PPI_MAX), 5513878Sgiacomo.travaglini@arm.com addrRangeSize(gic->params()->gicv4 ? 0x40000 : 0x20000) 5613531Sjairo.balart@metempsy.com{ 5713531Sjairo.balart@metempsy.com} 5813531Sjairo.balart@metempsy.com 5913531Sjairo.balart@metempsy.comvoid 6013531Sjairo.balart@metempsy.comGicv3Redistributor::init() 6113531Sjairo.balart@metempsy.com{ 6213531Sjairo.balart@metempsy.com distributor = gic->getDistributor(); 6313531Sjairo.balart@metempsy.com cpuInterface = gic->getCPUInterface(cpuId); 6413531Sjairo.balart@metempsy.com} 6513531Sjairo.balart@metempsy.com 6613531Sjairo.balart@metempsy.comvoid 6713531Sjairo.balart@metempsy.comGicv3Redistributor::initState() 6813531Sjairo.balart@metempsy.com{ 6913531Sjairo.balart@metempsy.com reset(); 7013531Sjairo.balart@metempsy.com} 7113531Sjairo.balart@metempsy.com 7213531Sjairo.balart@metempsy.comvoid 7313531Sjairo.balart@metempsy.comGicv3Redistributor::reset() 7413531Sjairo.balart@metempsy.com{ 7513531Sjairo.balart@metempsy.com peInLowPowerState = true; 7613531Sjairo.balart@metempsy.com std::fill(irqGroup.begin(), irqGroup.end(), 0); 7713531Sjairo.balart@metempsy.com std::fill(irqEnabled.begin(), irqEnabled.end(), false); 7813531Sjairo.balart@metempsy.com std::fill(irqPending.begin(), irqPending.end(), false); 7913531Sjairo.balart@metempsy.com std::fill(irqActive.begin(), irqActive.end(), false); 8013531Sjairo.balart@metempsy.com std::fill(irqPriority.begin(), irqPriority.end(), 0); 8113531Sjairo.balart@metempsy.com 8213531Sjairo.balart@metempsy.com // SGIs have edge-triggered behavior 8313531Sjairo.balart@metempsy.com for (uint32_t int_id = 0; int_id < Gicv3::SGI_MAX; int_id++) { 8413531Sjairo.balart@metempsy.com irqConfig[int_id] = Gicv3::INT_EDGE_TRIGGERED; 8513531Sjairo.balart@metempsy.com } 8613531Sjairo.balart@metempsy.com 8713531Sjairo.balart@metempsy.com std::fill(irqGrpmod.begin(), irqGrpmod.end(), 0); 8813531Sjairo.balart@metempsy.com std::fill(irqNsacr.begin(), irqNsacr.end(), 0); 8913531Sjairo.balart@metempsy.com DPG1S = false; 9013531Sjairo.balart@metempsy.com DPG1NS = false; 9113531Sjairo.balart@metempsy.com DPG0 = false; 9213690Sjairo.balart@metempsy.com EnableLPIs = false; 9313690Sjairo.balart@metempsy.com lpiConfigurationTablePtr = 0; 9413690Sjairo.balart@metempsy.com lpiIDBits = 0; 9513690Sjairo.balart@metempsy.com lpiPendingTablePtr = 0; 9613531Sjairo.balart@metempsy.com} 9713531Sjairo.balart@metempsy.com 9813531Sjairo.balart@metempsy.comuint64_t 9913531Sjairo.balart@metempsy.comGicv3Redistributor::read(Addr addr, size_t size, bool is_secure_access) 10013531Sjairo.balart@metempsy.com{ 10113531Sjairo.balart@metempsy.com if (GICR_IPRIORITYR.contains(addr)) { // Interrupt Priority Registers 10213531Sjairo.balart@metempsy.com uint64_t value = 0; 10313531Sjairo.balart@metempsy.com int first_intid = addr - GICR_IPRIORITYR.start(); 10413531Sjairo.balart@metempsy.com 10513531Sjairo.balart@metempsy.com for (int i = 0, int_id = first_intid; i < size; i++, int_id++) { 10613531Sjairo.balart@metempsy.com uint8_t prio = irqPriority[int_id]; 10713531Sjairo.balart@metempsy.com 10813531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 10913531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 11013531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 11113531Sjairo.balart@metempsy.com continue; 11213531Sjairo.balart@metempsy.com } else { 11313531Sjairo.balart@metempsy.com // NS view 11413531Sjairo.balart@metempsy.com prio = (prio << 1) & 0xff; 11513531Sjairo.balart@metempsy.com } 11613531Sjairo.balart@metempsy.com } 11713531Sjairo.balart@metempsy.com 11813531Sjairo.balart@metempsy.com value |= prio << (i * 8); 11913531Sjairo.balart@metempsy.com } 12013531Sjairo.balart@metempsy.com 12113531Sjairo.balart@metempsy.com return value; 12213531Sjairo.balart@metempsy.com } 12313531Sjairo.balart@metempsy.com 12413531Sjairo.balart@metempsy.com switch (addr) { 12513531Sjairo.balart@metempsy.com case GICR_CTLR: { // Control Register 12613531Sjairo.balart@metempsy.com uint64_t value = 0; 12713531Sjairo.balart@metempsy.com 12813531Sjairo.balart@metempsy.com if (DPG1S) { 12913531Sjairo.balart@metempsy.com value |= GICR_CTLR_DPG1S; 13013531Sjairo.balart@metempsy.com } 13113531Sjairo.balart@metempsy.com 13213531Sjairo.balart@metempsy.com if (DPG1NS) { 13313531Sjairo.balart@metempsy.com value |= GICR_CTLR_DPG1NS; 13413531Sjairo.balart@metempsy.com } 13513531Sjairo.balart@metempsy.com 13613531Sjairo.balart@metempsy.com if (DPG0) { 13713531Sjairo.balart@metempsy.com value |= GICR_CTLR_DPG0; 13813531Sjairo.balart@metempsy.com } 13913531Sjairo.balart@metempsy.com 14013690Sjairo.balart@metempsy.com if (EnableLPIs) { 14113690Sjairo.balart@metempsy.com value |= GICR_CTLR_ENABLE_LPIS; 14213690Sjairo.balart@metempsy.com } 14313690Sjairo.balart@metempsy.com 14413531Sjairo.balart@metempsy.com return value; 14513531Sjairo.balart@metempsy.com } 14613531Sjairo.balart@metempsy.com 14713531Sjairo.balart@metempsy.com case GICR_IIDR: // Implementer Identification Register 14813531Sjairo.balart@metempsy.com //return 0x43b; // r0p0 GIC-500 14913531Sjairo.balart@metempsy.com return 0; 15013531Sjairo.balart@metempsy.com 15113531Sjairo.balart@metempsy.com case GICR_TYPER: { // Type Register 15213531Sjairo.balart@metempsy.com /* 15313531Sjairo.balart@metempsy.com * Affinity_Value [63:32] == X 15413531Sjairo.balart@metempsy.com * (The identity of the PE associated with this Redistributor) 15513531Sjairo.balart@metempsy.com * CommonLPIAff [25:24] == 01 15613531Sjairo.balart@metempsy.com * (All Redistributors with the same Aff3 value must share an 15713531Sjairo.balart@metempsy.com * LPI Configuration table) 15813531Sjairo.balart@metempsy.com * Processor_Number [23:8] == X 15913531Sjairo.balart@metempsy.com * (A unique identifier for the PE) 16013531Sjairo.balart@metempsy.com * DPGS [5] == 1 16113531Sjairo.balart@metempsy.com * (GICR_CTLR.DPG* bits are supported) 16213531Sjairo.balart@metempsy.com * Last [4] == X 16313531Sjairo.balart@metempsy.com * (This Redistributor is the highest-numbered Redistributor in 16413531Sjairo.balart@metempsy.com * a series of contiguous Redistributor pages) 16513690Sjairo.balart@metempsy.com * DirectLPI [3] == 1 16613690Sjairo.balart@metempsy.com * (direct injection of LPIs supported) 16713531Sjairo.balart@metempsy.com * VLPIS [1] == 0 16813531Sjairo.balart@metempsy.com * (virtual LPIs not supported) 16913690Sjairo.balart@metempsy.com * PLPIS [0] == 1 17013690Sjairo.balart@metempsy.com * (physical LPIs supported) 17113531Sjairo.balart@metempsy.com */ 17213531Sjairo.balart@metempsy.com uint64_t affinity = getAffinity(); 17313531Sjairo.balart@metempsy.com int last = cpuId == (gic->getSystem()->numContexts() - 1); 17413531Sjairo.balart@metempsy.com return (affinity << 32) | (1 << 24) | (cpuId << 8) | 17513690Sjairo.balart@metempsy.com (1 << 5) | (last << 4) | (1 << 3) | (1 << 0); 17613531Sjairo.balart@metempsy.com } 17713531Sjairo.balart@metempsy.com 17813531Sjairo.balart@metempsy.com case GICR_WAKER: // Wake Register 17913531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 18013531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses 18113531Sjairo.balart@metempsy.com return 0; 18213531Sjairo.balart@metempsy.com } 18313531Sjairo.balart@metempsy.com 18413531Sjairo.balart@metempsy.com if (peInLowPowerState) { 18513531Sjairo.balart@metempsy.com return GICR_WAKER_ChildrenAsleep | GICR_WAKER_ProcessorSleep; 18613531Sjairo.balart@metempsy.com } else { 18713531Sjairo.balart@metempsy.com return 0; 18813531Sjairo.balart@metempsy.com } 18913531Sjairo.balart@metempsy.com 19013531Sjairo.balart@metempsy.com case GICR_PIDR0: { // Peripheral ID0 Register 19113756Sjairo.balart@metempsy.com return 0x92; // Part number, bits[7:0] 19213531Sjairo.balart@metempsy.com } 19313531Sjairo.balart@metempsy.com 19413531Sjairo.balart@metempsy.com case GICR_PIDR1: { // Peripheral ID1 Register 19513531Sjairo.balart@metempsy.com uint8_t des_0 = 0xB; // JEP106 identification code, bits[3:0] 19613531Sjairo.balart@metempsy.com uint8_t part_1 = 0x4; // Part number, bits[11:8] 19713531Sjairo.balart@metempsy.com return (des_0 << 4) | (part_1 << 0); 19813531Sjairo.balart@metempsy.com } 19913531Sjairo.balart@metempsy.com 20013531Sjairo.balart@metempsy.com case GICR_PIDR2: { // Peripheral ID2 Register 20113531Sjairo.balart@metempsy.com uint8_t arch_rev = 0x3; // 0x3 GICv3 20213531Sjairo.balart@metempsy.com uint8_t jedec = 0x1; // JEP code 20313531Sjairo.balart@metempsy.com uint8_t des_1 = 0x3; // JEP106 identification code, bits[6:4] 20413531Sjairo.balart@metempsy.com return (arch_rev << 4) | (jedec << 3) | (des_1 << 0); 20513531Sjairo.balart@metempsy.com } 20613531Sjairo.balart@metempsy.com 20713531Sjairo.balart@metempsy.com case GICR_PIDR3: // Peripheral ID3 Register 20813531Sjairo.balart@metempsy.com return 0x0; // Implementation defined 20913531Sjairo.balart@metempsy.com 21013531Sjairo.balart@metempsy.com case GICR_PIDR4: { // Peripheral ID4 Register 21113531Sjairo.balart@metempsy.com uint8_t size = 0x4; // 64 KB software visible page 21213531Sjairo.balart@metempsy.com uint8_t des_2 = 0x4; // ARM implementation 21313531Sjairo.balart@metempsy.com return (size << 4) | (des_2 << 0); 21413531Sjairo.balart@metempsy.com } 21513531Sjairo.balart@metempsy.com 21613531Sjairo.balart@metempsy.com case GICR_PIDR5: // Peripheral ID5 Register 21713531Sjairo.balart@metempsy.com case GICR_PIDR6: // Peripheral ID6 Register 21813531Sjairo.balart@metempsy.com case GICR_PIDR7: // Peripheral ID7 Register 21913531Sjairo.balart@metempsy.com return 0; // RES0 22013531Sjairo.balart@metempsy.com 22113531Sjairo.balart@metempsy.com case GICR_IGROUPR0: { // Interrupt Group Register 0 22213531Sjairo.balart@metempsy.com uint64_t value = 0; 22313531Sjairo.balart@metempsy.com 22413531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 22513531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses 22613531Sjairo.balart@metempsy.com return 0; 22713531Sjairo.balart@metempsy.com } 22813531Sjairo.balart@metempsy.com 22913531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 23013531Sjairo.balart@metempsy.com value |= (irqGroup[int_id] << int_id); 23113531Sjairo.balart@metempsy.com } 23213531Sjairo.balart@metempsy.com 23313531Sjairo.balart@metempsy.com return value; 23413531Sjairo.balart@metempsy.com } 23513531Sjairo.balart@metempsy.com 23613531Sjairo.balart@metempsy.com case GICR_ISENABLER0: // Interrupt Set-Enable Register 0 23713531Sjairo.balart@metempsy.com case GICR_ICENABLER0: { // Interrupt Clear-Enable Register 0 23813531Sjairo.balart@metempsy.com uint64_t value = 0; 23913531Sjairo.balart@metempsy.com 24013531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 24113531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 24213531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 24313531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 24413531Sjairo.balart@metempsy.com continue; 24513531Sjairo.balart@metempsy.com } 24613531Sjairo.balart@metempsy.com } 24713531Sjairo.balart@metempsy.com 24813531Sjairo.balart@metempsy.com if (irqEnabled[int_id]) { 24913531Sjairo.balart@metempsy.com value |= (1 << int_id); 25013531Sjairo.balart@metempsy.com } 25113531Sjairo.balart@metempsy.com } 25213531Sjairo.balart@metempsy.com 25313531Sjairo.balart@metempsy.com return value; 25413531Sjairo.balart@metempsy.com } 25513531Sjairo.balart@metempsy.com 25613531Sjairo.balart@metempsy.com case GICR_ISPENDR0: // Interrupt Set-Pending Register 0 25713531Sjairo.balart@metempsy.com case GICR_ICPENDR0: { // Interrupt Clear-Pending Register 0 25813531Sjairo.balart@metempsy.com uint64_t value = 0; 25913531Sjairo.balart@metempsy.com 26013531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 26113531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 26213531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 26313531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 26413531Sjairo.balart@metempsy.com continue; 26513531Sjairo.balart@metempsy.com } 26613531Sjairo.balart@metempsy.com } 26713531Sjairo.balart@metempsy.com 26813531Sjairo.balart@metempsy.com value |= (irqPending[int_id] << int_id); 26913531Sjairo.balart@metempsy.com } 27013531Sjairo.balart@metempsy.com 27113531Sjairo.balart@metempsy.com return value; 27213531Sjairo.balart@metempsy.com } 27313531Sjairo.balart@metempsy.com 27413531Sjairo.balart@metempsy.com case GICR_ISACTIVER0: // Interrupt Set-Active Register 0 27513531Sjairo.balart@metempsy.com case GICR_ICACTIVER0: { // Interrupt Clear-Active Register 0 27613531Sjairo.balart@metempsy.com uint64_t value = 0; 27713531Sjairo.balart@metempsy.com 27813531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 27913531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 28013531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 28113531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 28213531Sjairo.balart@metempsy.com continue; 28313531Sjairo.balart@metempsy.com } 28413531Sjairo.balart@metempsy.com } 28513531Sjairo.balart@metempsy.com 28613531Sjairo.balart@metempsy.com value |= irqActive[int_id] << int_id; 28713531Sjairo.balart@metempsy.com } 28813531Sjairo.balart@metempsy.com 28913531Sjairo.balart@metempsy.com return value; 29013531Sjairo.balart@metempsy.com } 29113531Sjairo.balart@metempsy.com 29213531Sjairo.balart@metempsy.com case GICR_ICFGR0: // SGI Configuration Register 29313531Sjairo.balart@metempsy.com case GICR_ICFGR1: { // PPI Configuration Register 29413531Sjairo.balart@metempsy.com uint64_t value = 0; 29513531Sjairo.balart@metempsy.com uint32_t first_int_id = addr == GICR_ICFGR0 ? 0 : Gicv3::SGI_MAX; 29613531Sjairo.balart@metempsy.com 29713531Sjairo.balart@metempsy.com for (int i = 0, int_id = first_int_id; i < 32; 29813756Sjairo.balart@metempsy.com i = i + 2, int_id++) { 29913531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 30013531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 30113531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 30213531Sjairo.balart@metempsy.com continue; 30313531Sjairo.balart@metempsy.com } 30413531Sjairo.balart@metempsy.com } 30513531Sjairo.balart@metempsy.com 30613531Sjairo.balart@metempsy.com if (irqConfig[int_id] == Gicv3::INT_EDGE_TRIGGERED) { 30713531Sjairo.balart@metempsy.com value |= (0x2) << i; 30813531Sjairo.balart@metempsy.com } 30913531Sjairo.balart@metempsy.com } 31013531Sjairo.balart@metempsy.com 31113531Sjairo.balart@metempsy.com return value; 31213531Sjairo.balart@metempsy.com } 31313531Sjairo.balart@metempsy.com 31413531Sjairo.balart@metempsy.com case GICR_IGRPMODR0: { // Interrupt Group Modifier Register 0 31513531Sjairo.balart@metempsy.com uint64_t value = 0; 31613531Sjairo.balart@metempsy.com 31713531Sjairo.balart@metempsy.com if (distributor->DS) { 31813531Sjairo.balart@metempsy.com value = 0; 31913531Sjairo.balart@metempsy.com } else { 32013531Sjairo.balart@metempsy.com if (!is_secure_access) { 32113531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses 32213531Sjairo.balart@metempsy.com value = 0; 32313531Sjairo.balart@metempsy.com } else { 32413531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 32513531Sjairo.balart@metempsy.com value |= irqGrpmod[int_id] << int_id; 32613531Sjairo.balart@metempsy.com } 32713531Sjairo.balart@metempsy.com } 32813531Sjairo.balart@metempsy.com } 32913531Sjairo.balart@metempsy.com 33013531Sjairo.balart@metempsy.com return value; 33113531Sjairo.balart@metempsy.com } 33213531Sjairo.balart@metempsy.com 33313531Sjairo.balart@metempsy.com case GICR_NSACR: { // Non-secure Access Control Register 33413531Sjairo.balart@metempsy.com uint64_t value = 0; 33513531Sjairo.balart@metempsy.com 33613531Sjairo.balart@metempsy.com if (distributor->DS) { 33713531Sjairo.balart@metempsy.com // RAZ/WI 33813531Sjairo.balart@metempsy.com value = 0; 33913531Sjairo.balart@metempsy.com } else { 34013531Sjairo.balart@metempsy.com if (!is_secure_access) { 34113531Sjairo.balart@metempsy.com // RAZ/WI 34213531Sjairo.balart@metempsy.com value = 0; 34313531Sjairo.balart@metempsy.com } else { 34413531Sjairo.balart@metempsy.com for (int i = 0, int_id = 0; i < 8 * size; 34513756Sjairo.balart@metempsy.com i = i + 2, int_id++) { 34613531Sjairo.balart@metempsy.com value |= irqNsacr[int_id] << i; 34713531Sjairo.balart@metempsy.com } 34813531Sjairo.balart@metempsy.com } 34913531Sjairo.balart@metempsy.com } 35013531Sjairo.balart@metempsy.com 35113531Sjairo.balart@metempsy.com return value; 35213531Sjairo.balart@metempsy.com } 35313531Sjairo.balart@metempsy.com 35413690Sjairo.balart@metempsy.com case GICR_PROPBASER: // Redistributor Properties Base Address Register 35513690Sjairo.balart@metempsy.com // OuterCache, bits [58:56] 35613690Sjairo.balart@metempsy.com // 000 Memory type defined in InnerCache field 35713690Sjairo.balart@metempsy.com // Physical_Address, bits [51:12] 35813690Sjairo.balart@metempsy.com // Bits [51:12] of the physical address containing the LPI 35913690Sjairo.balart@metempsy.com // Configuration table 36013690Sjairo.balart@metempsy.com // Shareability, bits [11:10] 36113690Sjairo.balart@metempsy.com // 00 Non-shareable 36213690Sjairo.balart@metempsy.com // InnerCache, bits [9:7] 36313690Sjairo.balart@metempsy.com // 000 Device-nGnRnE 36413690Sjairo.balart@metempsy.com // IDbits, bits [4:0] 36513690Sjairo.balart@metempsy.com // limited by GICD_TYPER.IDbits 36613690Sjairo.balart@metempsy.com return lpiConfigurationTablePtr | lpiIDBits; 36713690Sjairo.balart@metempsy.com 36813690Sjairo.balart@metempsy.com // Redistributor LPI Pending Table Base Address Register 36913690Sjairo.balart@metempsy.com case GICR_PENDBASER: 37013690Sjairo.balart@metempsy.com // PTZ, bit [62] 37113690Sjairo.balart@metempsy.com // Pending Table Zero 37213690Sjairo.balart@metempsy.com // OuterCache, bits [58:56] 37313690Sjairo.balart@metempsy.com // 000 Memory type defined in InnerCache field 37413690Sjairo.balart@metempsy.com // Physical_Address, bits [51:16] 37513690Sjairo.balart@metempsy.com // Bits [51:16] of the physical address containing the LPI Pending 37613690Sjairo.balart@metempsy.com // table 37713690Sjairo.balart@metempsy.com // Shareability, bits [11:10] 37813690Sjairo.balart@metempsy.com // 00 Non-shareable 37913690Sjairo.balart@metempsy.com // InnerCache, bits [9:7] 38013690Sjairo.balart@metempsy.com // 000 Device-nGnRnE 38113690Sjairo.balart@metempsy.com return lpiPendingTablePtr; 38213690Sjairo.balart@metempsy.com 38313690Sjairo.balart@metempsy.com // Redistributor Synchronize Register 38413690Sjairo.balart@metempsy.com case GICR_SYNCR: 38513690Sjairo.balart@metempsy.com return 0; 38613690Sjairo.balart@metempsy.com 38713531Sjairo.balart@metempsy.com default: 38813531Sjairo.balart@metempsy.com panic("Gicv3Redistributor::read(): invalid offset %#x\n", addr); 38913531Sjairo.balart@metempsy.com break; 39013531Sjairo.balart@metempsy.com } 39113531Sjairo.balart@metempsy.com} 39213531Sjairo.balart@metempsy.com 39313531Sjairo.balart@metempsy.comvoid 39413531Sjairo.balart@metempsy.comGicv3Redistributor::write(Addr addr, uint64_t data, size_t size, 39513531Sjairo.balart@metempsy.com bool is_secure_access) 39613531Sjairo.balart@metempsy.com{ 39713531Sjairo.balart@metempsy.com if (GICR_IPRIORITYR.contains(addr)) { // Interrupt Priority Registers 39813531Sjairo.balart@metempsy.com int first_intid = addr - GICR_IPRIORITYR.start(); 39913531Sjairo.balart@metempsy.com 40013531Sjairo.balart@metempsy.com for (int i = 0, int_id = first_intid; i < size; i++, int_id++) { 40113531Sjairo.balart@metempsy.com uint8_t prio = bits(data, (i + 1) * 8 - 1, (i * 8)); 40213531Sjairo.balart@metempsy.com 40313531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 40413531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 40513531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 40613531Sjairo.balart@metempsy.com continue; 40713531Sjairo.balart@metempsy.com } else { 40813531Sjairo.balart@metempsy.com // NS view 40913531Sjairo.balart@metempsy.com prio = 0x80 | (prio >> 1); 41013531Sjairo.balart@metempsy.com } 41113531Sjairo.balart@metempsy.com } 41213531Sjairo.balart@metempsy.com 41313531Sjairo.balart@metempsy.com irqPriority[int_id] = prio; 41413531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write(): " 41513531Sjairo.balart@metempsy.com "int_id %d priority %d\n", int_id, irqPriority[int_id]); 41613531Sjairo.balart@metempsy.com } 41713531Sjairo.balart@metempsy.com 41813531Sjairo.balart@metempsy.com return; 41913531Sjairo.balart@metempsy.com } 42013531Sjairo.balart@metempsy.com 42113531Sjairo.balart@metempsy.com switch (addr) { 42213531Sjairo.balart@metempsy.com case GICR_CTLR: { 42313690Sjairo.balart@metempsy.com // GICR_TYPER.LPIS is 0 so EnableLPIs is RES0 42413690Sjairo.balart@metempsy.com EnableLPIs = data & GICR_CTLR_ENABLE_LPIS; 42513531Sjairo.balart@metempsy.com DPG1S = data & GICR_CTLR_DPG1S; 42613531Sjairo.balart@metempsy.com DPG1NS = data & GICR_CTLR_DPG1NS; 42713531Sjairo.balart@metempsy.com DPG0 = data & GICR_CTLR_DPG0; 42813531Sjairo.balart@metempsy.com break; 42913531Sjairo.balart@metempsy.com } 43013531Sjairo.balart@metempsy.com 43113531Sjairo.balart@metempsy.com case GICR_WAKER: // Wake Register 43213531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 43313531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses 43413531Sjairo.balart@metempsy.com return; 43513531Sjairo.balart@metempsy.com } 43613531Sjairo.balart@metempsy.com 43713531Sjairo.balart@metempsy.com if (not peInLowPowerState and 43813756Sjairo.balart@metempsy.com (data & GICR_WAKER_ProcessorSleep)) { 43913531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write(): " 44013531Sjairo.balart@metempsy.com "PE entering in low power state\n"); 44113531Sjairo.balart@metempsy.com } else if (peInLowPowerState and 44213756Sjairo.balart@metempsy.com not(data & GICR_WAKER_ProcessorSleep)) { 44313531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write(): powering up PE\n"); 44413531Sjairo.balart@metempsy.com } 44513531Sjairo.balart@metempsy.com 44613531Sjairo.balart@metempsy.com peInLowPowerState = data & GICR_WAKER_ProcessorSleep; 44713531Sjairo.balart@metempsy.com break; 44813531Sjairo.balart@metempsy.com 44913531Sjairo.balart@metempsy.com case GICR_IGROUPR0: // Interrupt Group Register 0 45013531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 45113531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses 45213531Sjairo.balart@metempsy.com return; 45313531Sjairo.balart@metempsy.com } 45413531Sjairo.balart@metempsy.com 45513531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 45613531Sjairo.balart@metempsy.com irqGroup[int_id] = data & (1 << int_id) ? 1 : 0; 45713531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write(): " 45813531Sjairo.balart@metempsy.com "int_id %d group %d\n", int_id, irqGroup[int_id]); 45913531Sjairo.balart@metempsy.com } 46013531Sjairo.balart@metempsy.com 46113531Sjairo.balart@metempsy.com break; 46213531Sjairo.balart@metempsy.com 46313531Sjairo.balart@metempsy.com case GICR_ISENABLER0: // Interrupt Set-Enable Register 0 46413531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 46513531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 46613531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 46713531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 46813531Sjairo.balart@metempsy.com continue; 46913531Sjairo.balart@metempsy.com } 47013531Sjairo.balart@metempsy.com } 47113531Sjairo.balart@metempsy.com 47213531Sjairo.balart@metempsy.com bool enable = data & (1 << int_id) ? 1 : 0; 47313531Sjairo.balart@metempsy.com 47413531Sjairo.balart@metempsy.com if (enable) { 47513531Sjairo.balart@metempsy.com irqEnabled[int_id] = true; 47613531Sjairo.balart@metempsy.com } 47713531Sjairo.balart@metempsy.com 47813531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write(): " 47913531Sjairo.balart@metempsy.com "int_id %d enable %i\n", int_id, irqEnabled[int_id]); 48013531Sjairo.balart@metempsy.com } 48113531Sjairo.balart@metempsy.com 48213531Sjairo.balart@metempsy.com break; 48313531Sjairo.balart@metempsy.com 48413531Sjairo.balart@metempsy.com case GICR_ICENABLER0: // Interrupt Clear-Enable Register 0 48513531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 48613531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 48713531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 48813531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 48913531Sjairo.balart@metempsy.com continue; 49013531Sjairo.balart@metempsy.com } 49113531Sjairo.balart@metempsy.com } 49213531Sjairo.balart@metempsy.com 49313531Sjairo.balart@metempsy.com bool disable = data & (1 << int_id) ? 1 : 0; 49413531Sjairo.balart@metempsy.com 49513531Sjairo.balart@metempsy.com if (disable) { 49613531Sjairo.balart@metempsy.com irqEnabled[int_id] = false; 49713531Sjairo.balart@metempsy.com } 49813531Sjairo.balart@metempsy.com 49913531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write(): " 50013531Sjairo.balart@metempsy.com "int_id %d enable %i\n", int_id, irqEnabled[int_id]); 50113531Sjairo.balart@metempsy.com } 50213531Sjairo.balart@metempsy.com 50313531Sjairo.balart@metempsy.com break; 50413531Sjairo.balart@metempsy.com 50513531Sjairo.balart@metempsy.com case GICR_ISPENDR0: // Interrupt Set-Pending Register 0 50613531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 50713531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 50813531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 50913531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 51013531Sjairo.balart@metempsy.com continue; 51113531Sjairo.balart@metempsy.com } 51213531Sjairo.balart@metempsy.com } 51313531Sjairo.balart@metempsy.com 51413531Sjairo.balart@metempsy.com bool pending = data & (1 << int_id) ? 1 : 0; 51513531Sjairo.balart@metempsy.com 51613531Sjairo.balart@metempsy.com if (pending) { 51713531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write() " 51813531Sjairo.balart@metempsy.com "(GICR_ISPENDR0): int_id %d (PPI) " 51913531Sjairo.balart@metempsy.com "pending bit set\n", int_id); 52013531Sjairo.balart@metempsy.com irqPending[int_id] = true; 52113531Sjairo.balart@metempsy.com } 52213531Sjairo.balart@metempsy.com } 52313531Sjairo.balart@metempsy.com 52413531Sjairo.balart@metempsy.com updateAndInformCPUInterface(); 52513531Sjairo.balart@metempsy.com break; 52613531Sjairo.balart@metempsy.com 52713531Sjairo.balart@metempsy.com case GICR_ICPENDR0:// Interrupt Clear-Pending Register 0 52813531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 52913531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 53013531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 53113531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 53213531Sjairo.balart@metempsy.com continue; 53313531Sjairo.balart@metempsy.com } 53413531Sjairo.balart@metempsy.com } 53513531Sjairo.balart@metempsy.com 53613531Sjairo.balart@metempsy.com bool clear = data & (1 << int_id) ? 1 : 0; 53713531Sjairo.balart@metempsy.com 53813531Sjairo.balart@metempsy.com if (clear) { 53913531Sjairo.balart@metempsy.com irqPending[int_id] = false; 54013531Sjairo.balart@metempsy.com } 54113531Sjairo.balart@metempsy.com } 54213531Sjairo.balart@metempsy.com 54313531Sjairo.balart@metempsy.com break; 54413531Sjairo.balart@metempsy.com 54513531Sjairo.balart@metempsy.com case GICR_ISACTIVER0: // Interrupt Set-Active Register 0 54613531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 54713531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 54813531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 54913531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 55013531Sjairo.balart@metempsy.com continue; 55113531Sjairo.balart@metempsy.com } 55213531Sjairo.balart@metempsy.com } 55313531Sjairo.balart@metempsy.com 55413531Sjairo.balart@metempsy.com bool activate = data & (1 << int_id) ? 1 : 0; 55513531Sjairo.balart@metempsy.com 55613531Sjairo.balart@metempsy.com if (activate) { 55713531Sjairo.balart@metempsy.com if (!irqActive[int_id]) { 55813531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write(): " 55913531Sjairo.balart@metempsy.com "int_id %d active set\n", int_id); 56013531Sjairo.balart@metempsy.com } 56113531Sjairo.balart@metempsy.com 56213531Sjairo.balart@metempsy.com irqActive[int_id] = true; 56313531Sjairo.balart@metempsy.com } 56413531Sjairo.balart@metempsy.com } 56513531Sjairo.balart@metempsy.com 56613531Sjairo.balart@metempsy.com break; 56713531Sjairo.balart@metempsy.com 56813531Sjairo.balart@metempsy.com case GICR_ICACTIVER0: // Interrupt Clear-Active Register 0 56913531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 57013531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 57113531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 57213531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 57313531Sjairo.balart@metempsy.com continue; 57413531Sjairo.balart@metempsy.com } 57513531Sjairo.balart@metempsy.com } 57613531Sjairo.balart@metempsy.com 57713531Sjairo.balart@metempsy.com bool clear = data & (1 << int_id) ? 1 : 0; 57813531Sjairo.balart@metempsy.com 57913531Sjairo.balart@metempsy.com if (clear) { 58013531Sjairo.balart@metempsy.com if (irqActive[int_id]) { 58113531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write(): " 58213531Sjairo.balart@metempsy.com "int_id %d active cleared\n", int_id); 58313531Sjairo.balart@metempsy.com } 58413531Sjairo.balart@metempsy.com 58513531Sjairo.balart@metempsy.com irqActive[int_id] = false; 58613531Sjairo.balart@metempsy.com } 58713531Sjairo.balart@metempsy.com } 58813531Sjairo.balart@metempsy.com 58913531Sjairo.balart@metempsy.com break; 59013531Sjairo.balart@metempsy.com 59113531Sjairo.balart@metempsy.com case GICR_ICFGR1: { // PPI Configuration Register 59213531Sjairo.balart@metempsy.com int first_intid = Gicv3::SGI_MAX; 59313531Sjairo.balart@metempsy.com 59413531Sjairo.balart@metempsy.com for (int i = 0, int_id = first_intid; i < 8 * size; 59513756Sjairo.balart@metempsy.com i = i + 2, int_id++) { 59613531Sjairo.balart@metempsy.com if (!distributor->DS && !is_secure_access) { 59713531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses for secure interrupts 59813531Sjairo.balart@metempsy.com if (getIntGroup(int_id) != Gicv3::G1NS) { 59913531Sjairo.balart@metempsy.com continue; 60013531Sjairo.balart@metempsy.com } 60113531Sjairo.balart@metempsy.com } 60213531Sjairo.balart@metempsy.com 60313756Sjairo.balart@metempsy.com irqConfig[int_id] = data & (0x2 << i) ? 60413756Sjairo.balart@metempsy.com Gicv3::INT_EDGE_TRIGGERED : 60513756Sjairo.balart@metempsy.com Gicv3::INT_LEVEL_SENSITIVE; 60613531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::write(): " 60713531Sjairo.balart@metempsy.com "int_id %d (PPI) config %d\n", 60813531Sjairo.balart@metempsy.com int_id, irqConfig[int_id]); 60913531Sjairo.balart@metempsy.com } 61013531Sjairo.balart@metempsy.com 61113531Sjairo.balart@metempsy.com break; 61213531Sjairo.balart@metempsy.com } 61313531Sjairo.balart@metempsy.com 61413531Sjairo.balart@metempsy.com case GICR_IGRPMODR0: { // Interrupt Group Modifier Register 0 61513531Sjairo.balart@metempsy.com if (distributor->DS) { 61613531Sjairo.balart@metempsy.com // RAZ/WI if secutiry disabled 61713531Sjairo.balart@metempsy.com } else { 61813531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < 8 * size; int_id++) { 61913531Sjairo.balart@metempsy.com if (!is_secure_access) { 62013531Sjairo.balart@metempsy.com // RAZ/WI for non-secure accesses 62113531Sjairo.balart@metempsy.com continue; 62213531Sjairo.balart@metempsy.com } 62313531Sjairo.balart@metempsy.com 62413531Sjairo.balart@metempsy.com irqGrpmod[int_id] = data & (1 << int_id); 62513531Sjairo.balart@metempsy.com } 62613531Sjairo.balart@metempsy.com } 62713531Sjairo.balart@metempsy.com 62813531Sjairo.balart@metempsy.com break; 62913531Sjairo.balart@metempsy.com } 63013531Sjairo.balart@metempsy.com 63113531Sjairo.balart@metempsy.com case GICR_NSACR: { // Non-secure Access Control Register 63213531Sjairo.balart@metempsy.com if (distributor->DS) { 63313531Sjairo.balart@metempsy.com // RAZ/WI 63413531Sjairo.balart@metempsy.com } else { 63513531Sjairo.balart@metempsy.com if (!is_secure_access) { 63613531Sjairo.balart@metempsy.com // RAZ/WI 63713531Sjairo.balart@metempsy.com } else { 63813531Sjairo.balart@metempsy.com for (int i = 0, int_id = 0; i < 8 * size; 63913756Sjairo.balart@metempsy.com i = i + 2, int_id++) { 64013531Sjairo.balart@metempsy.com irqNsacr[int_id] = (data >> i) & 0x3; 64113531Sjairo.balart@metempsy.com } 64213531Sjairo.balart@metempsy.com } 64313531Sjairo.balart@metempsy.com } 64413531Sjairo.balart@metempsy.com 64513531Sjairo.balart@metempsy.com break; 64613531Sjairo.balart@metempsy.com } 64713531Sjairo.balart@metempsy.com 64813690Sjairo.balart@metempsy.com case GICR_SETLPIR: // Set LPI Pending Register 64913690Sjairo.balart@metempsy.com setClrLPI(data, true); 65013690Sjairo.balart@metempsy.com break; 65113690Sjairo.balart@metempsy.com 65213690Sjairo.balart@metempsy.com case GICR_CLRLPIR: // Clear LPI Pending Register 65313690Sjairo.balart@metempsy.com setClrLPI(data, false); 65413690Sjairo.balart@metempsy.com break; 65513690Sjairo.balart@metempsy.com 65613690Sjairo.balart@metempsy.com case GICR_PROPBASER: { // Redistributor Properties Base Address Register 65713690Sjairo.balart@metempsy.com // OuterCache, bits [58:56] 65813690Sjairo.balart@metempsy.com // 000 Memory type defined in InnerCache field 65913690Sjairo.balart@metempsy.com // Physical_Address, bits [51:12] 66013690Sjairo.balart@metempsy.com // Bits [51:12] of the physical address containing the LPI 66113690Sjairo.balart@metempsy.com // Configuration table 66213690Sjairo.balart@metempsy.com // Shareability, bits [11:10] 66313690Sjairo.balart@metempsy.com // 00 Non-shareable 66413690Sjairo.balart@metempsy.com // InnerCache, bits [9:7] 66513690Sjairo.balart@metempsy.com // 000 Device-nGnRnE 66613690Sjairo.balart@metempsy.com // IDbits, bits [4:0] 66713690Sjairo.balart@metempsy.com // limited by GICD_TYPER.IDbits (= 0xf) 66813690Sjairo.balart@metempsy.com lpiConfigurationTablePtr = data & 0xFFFFFFFFFF000; 66913690Sjairo.balart@metempsy.com lpiIDBits = data & 0x1f; 67013690Sjairo.balart@metempsy.com 67113690Sjairo.balart@metempsy.com // 0xf here matches the value of GICD_TYPER.IDbits. 67213690Sjairo.balart@metempsy.com // TODO - make GICD_TYPER.IDbits a parameter instead of a hardcoded 67313690Sjairo.balart@metempsy.com // value 67413690Sjairo.balart@metempsy.com if (lpiIDBits > 0xf) { 67513690Sjairo.balart@metempsy.com lpiIDBits = 0xf; 67613690Sjairo.balart@metempsy.com } 67713690Sjairo.balart@metempsy.com 67813690Sjairo.balart@metempsy.com break; 67913690Sjairo.balart@metempsy.com } 68013690Sjairo.balart@metempsy.com 68113690Sjairo.balart@metempsy.com // Redistributor LPI Pending Table Base Address Register 68213690Sjairo.balart@metempsy.com case GICR_PENDBASER: 68313690Sjairo.balart@metempsy.com // PTZ, bit [62] 68413690Sjairo.balart@metempsy.com // Pending Table Zero 68513690Sjairo.balart@metempsy.com // OuterCache, bits [58:56] 68613690Sjairo.balart@metempsy.com // 000 Memory type defined in InnerCache field 68713690Sjairo.balart@metempsy.com // Physical_Address, bits [51:16] 68813690Sjairo.balart@metempsy.com // Bits [51:16] of the physical address containing the LPI Pending 68913690Sjairo.balart@metempsy.com // table 69013690Sjairo.balart@metempsy.com // Shareability, bits [11:10] 69113690Sjairo.balart@metempsy.com // 00 Non-shareable 69213690Sjairo.balart@metempsy.com // InnerCache, bits [9:7] 69313690Sjairo.balart@metempsy.com // 000 Device-nGnRnE 69413690Sjairo.balart@metempsy.com lpiPendingTablePtr = data & 0xFFFFFFFFF0000; 69513690Sjairo.balart@metempsy.com break; 69613690Sjairo.balart@metempsy.com 69713690Sjairo.balart@metempsy.com case GICR_INVLPIR: { // Redistributor Invalidate LPI Register 69813921Sgiacomo.travaglini@arm.com // Do nothing: no caching supported 69913690Sjairo.balart@metempsy.com break; 70013690Sjairo.balart@metempsy.com } 70113690Sjairo.balart@metempsy.com 70213690Sjairo.balart@metempsy.com case GICR_INVALLR: { // Redistributor Invalidate All Register 70313921Sgiacomo.travaglini@arm.com // Do nothing: no caching supported 70413690Sjairo.balart@metempsy.com break; 70513690Sjairo.balart@metempsy.com } 70613690Sjairo.balart@metempsy.com 70713531Sjairo.balart@metempsy.com default: 70813531Sjairo.balart@metempsy.com panic("Gicv3Redistributor::write(): invalid offset %#x\n", addr); 70913531Sjairo.balart@metempsy.com break; 71013531Sjairo.balart@metempsy.com } 71113531Sjairo.balart@metempsy.com} 71213531Sjairo.balart@metempsy.com 71313531Sjairo.balart@metempsy.comvoid 71413531Sjairo.balart@metempsy.comGicv3Redistributor::sendPPInt(uint32_t int_id) 71513531Sjairo.balart@metempsy.com{ 71613531Sjairo.balart@metempsy.com assert((int_id >= Gicv3::SGI_MAX) && 71713531Sjairo.balart@metempsy.com (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX)); 71813531Sjairo.balart@metempsy.com irqPending[int_id] = true; 71913531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3Redistributor::sendPPInt(): " 72013531Sjairo.balart@metempsy.com "int_id %d (PPI) pending bit set\n", int_id); 72113531Sjairo.balart@metempsy.com updateAndInformCPUInterface(); 72213531Sjairo.balart@metempsy.com} 72313531Sjairo.balart@metempsy.com 72413531Sjairo.balart@metempsy.comvoid 72513531Sjairo.balart@metempsy.comGicv3Redistributor::sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns) 72613531Sjairo.balart@metempsy.com{ 72713531Sjairo.balart@metempsy.com assert(int_id < Gicv3::SGI_MAX); 72813531Sjairo.balart@metempsy.com Gicv3::GroupId int_group = getIntGroup(int_id); 72913531Sjairo.balart@metempsy.com 73013531Sjairo.balart@metempsy.com // asked for secure group 1 73113531Sjairo.balart@metempsy.com // configured as group 0 73213531Sjairo.balart@metempsy.com // send group 0 73313531Sjairo.balart@metempsy.com if (int_group == Gicv3::G0S && group == Gicv3::G1S) { 73413531Sjairo.balart@metempsy.com group = Gicv3::G0S; 73513531Sjairo.balart@metempsy.com } 73613531Sjairo.balart@metempsy.com 73713531Sjairo.balart@metempsy.com if (group == Gicv3::G0S and int_group != Gicv3::G0S) { 73813531Sjairo.balart@metempsy.com return; 73913531Sjairo.balart@metempsy.com } 74013531Sjairo.balart@metempsy.com 74113531Sjairo.balart@metempsy.com if (ns && distributor->DS == 0) { 74213531Sjairo.balart@metempsy.com int nsaccess = irqNsacr[int_id]; 74313531Sjairo.balart@metempsy.com 74413531Sjairo.balart@metempsy.com if ((int_group == Gicv3::G0S && nsaccess < 1) || 74513756Sjairo.balart@metempsy.com (int_group == Gicv3::G1S && nsaccess < 2)) { 74613531Sjairo.balart@metempsy.com return; 74713531Sjairo.balart@metempsy.com } 74813531Sjairo.balart@metempsy.com } 74913531Sjairo.balart@metempsy.com 75013531Sjairo.balart@metempsy.com irqPending[int_id] = true; 75113531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3ReDistributor::sendSGI(): " 75213531Sjairo.balart@metempsy.com "int_id %d (SGI) pending bit set\n", int_id); 75313531Sjairo.balart@metempsy.com updateAndInformCPUInterface(); 75413531Sjairo.balart@metempsy.com} 75513531Sjairo.balart@metempsy.com 75613531Sjairo.balart@metempsy.comGicv3::IntStatus 75713756Sjairo.balart@metempsy.comGicv3Redistributor::intStatus(uint32_t int_id) const 75813531Sjairo.balart@metempsy.com{ 75913531Sjairo.balart@metempsy.com assert(int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX); 76013531Sjairo.balart@metempsy.com 76113531Sjairo.balart@metempsy.com if (irqPending[int_id]) { 76213531Sjairo.balart@metempsy.com if (irqActive[int_id]) { 76313531Sjairo.balart@metempsy.com return Gicv3::INT_ACTIVE_PENDING; 76413531Sjairo.balart@metempsy.com } 76513531Sjairo.balart@metempsy.com 76613531Sjairo.balart@metempsy.com return Gicv3::INT_PENDING; 76713531Sjairo.balart@metempsy.com } else if (irqActive[int_id]) { 76813531Sjairo.balart@metempsy.com return Gicv3::INT_ACTIVE; 76913531Sjairo.balart@metempsy.com } else { 77013531Sjairo.balart@metempsy.com return Gicv3::INT_INACTIVE; 77113531Sjairo.balart@metempsy.com } 77213531Sjairo.balart@metempsy.com} 77313531Sjairo.balart@metempsy.com 77413531Sjairo.balart@metempsy.com/* 77513531Sjairo.balart@metempsy.com * Recalculate the highest priority pending interrupt after a 77613531Sjairo.balart@metempsy.com * change to redistributor state. 77713531Sjairo.balart@metempsy.com */ 77813531Sjairo.balart@metempsy.comvoid 77913531Sjairo.balart@metempsy.comGicv3Redistributor::update() 78013531Sjairo.balart@metempsy.com{ 78113531Sjairo.balart@metempsy.com bool new_hppi = false; 78213531Sjairo.balart@metempsy.com 78313531Sjairo.balart@metempsy.com for (int int_id = 0; int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX; int_id++) { 78413531Sjairo.balart@metempsy.com Gicv3::GroupId int_group = getIntGroup(int_id); 78513531Sjairo.balart@metempsy.com bool group_enabled = distributor->groupEnabled(int_group); 78613531Sjairo.balart@metempsy.com 78713531Sjairo.balart@metempsy.com if (irqPending[int_id] && irqEnabled[int_id] && 78813531Sjairo.balart@metempsy.com !irqActive[int_id] && group_enabled) { 78913531Sjairo.balart@metempsy.com if ((irqPriority[int_id] < cpuInterface->hppi.prio) || 79013756Sjairo.balart@metempsy.com /* 79113756Sjairo.balart@metempsy.com * Multiple pending ints with same priority. 79213756Sjairo.balart@metempsy.com * Implementation choice which one to signal. 79313756Sjairo.balart@metempsy.com * Our implementation selects the one with the lower id. 79413756Sjairo.balart@metempsy.com */ 79513756Sjairo.balart@metempsy.com (irqPriority[int_id] == cpuInterface->hppi.prio && 79613756Sjairo.balart@metempsy.com int_id < cpuInterface->hppi.intid)) { 79713531Sjairo.balart@metempsy.com cpuInterface->hppi.intid = int_id; 79813531Sjairo.balart@metempsy.com cpuInterface->hppi.prio = irqPriority[int_id]; 79913531Sjairo.balart@metempsy.com cpuInterface->hppi.group = int_group; 80013531Sjairo.balart@metempsy.com new_hppi = true; 80113531Sjairo.balart@metempsy.com } 80213531Sjairo.balart@metempsy.com } 80313531Sjairo.balart@metempsy.com } 80413531Sjairo.balart@metempsy.com 80513690Sjairo.balart@metempsy.com // Check LPIs 80613920Sgiacomo.travaglini@arm.com if (EnableLPIs) { 80713921Sgiacomo.travaglini@arm.com ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId); 80813921Sgiacomo.travaglini@arm.com 80913920Sgiacomo.travaglini@arm.com const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1); 81013921Sgiacomo.travaglini@arm.com const uint32_t number_lpis = largest_lpi_id - SMALLEST_LPI_ID + 1; 81113921Sgiacomo.travaglini@arm.com 81213921Sgiacomo.travaglini@arm.com uint8_t lpi_pending_table[largest_lpi_id / 8]; 81313921Sgiacomo.travaglini@arm.com uint8_t lpi_config_table[number_lpis]; 81413921Sgiacomo.travaglini@arm.com 81513920Sgiacomo.travaglini@arm.com tc->getPhysProxy().readBlob(lpiPendingTablePtr, 81613920Sgiacomo.travaglini@arm.com (uint8_t *) lpi_pending_table, 81713920Sgiacomo.travaglini@arm.com sizeof(lpi_pending_table)); 81813919Sgiacomo.travaglini@arm.com 81913921Sgiacomo.travaglini@arm.com tc->getPhysProxy().readBlob(lpiConfigurationTablePtr, 82013921Sgiacomo.travaglini@arm.com (uint8_t*) lpi_config_table, 82113921Sgiacomo.travaglini@arm.com sizeof(lpi_config_table)); 82213921Sgiacomo.travaglini@arm.com 82313920Sgiacomo.travaglini@arm.com for (int lpi_id = SMALLEST_LPI_ID; lpi_id < largest_lpi_id; 82413920Sgiacomo.travaglini@arm.com lpi_id++) { 82513920Sgiacomo.travaglini@arm.com uint32_t lpi_pending_entry_byte = lpi_id / 8; 82613920Sgiacomo.travaglini@arm.com uint8_t lpi_pending_entry_bit_position = lpi_id % 8; 82713920Sgiacomo.travaglini@arm.com bool lpi_is_pending = lpi_pending_table[lpi_pending_entry_byte] & 82813920Sgiacomo.travaglini@arm.com 1 << lpi_pending_entry_bit_position; 82913920Sgiacomo.travaglini@arm.com uint32_t lpi_configuration_entry_index = lpi_id - SMALLEST_LPI_ID; 83013921Sgiacomo.travaglini@arm.com 83113921Sgiacomo.travaglini@arm.com LPIConfigurationTableEntry config_entry = 83213921Sgiacomo.travaglini@arm.com lpi_config_table[lpi_configuration_entry_index]; 83313921Sgiacomo.travaglini@arm.com 83413921Sgiacomo.travaglini@arm.com bool lpi_is_enable = config_entry.enable; 83513921Sgiacomo.travaglini@arm.com 83613920Sgiacomo.travaglini@arm.com // LPIs are always Non-secure Group 1 interrupts, 83713920Sgiacomo.travaglini@arm.com // in a system where two Security states are enabled. 83813920Sgiacomo.travaglini@arm.com Gicv3::GroupId lpi_group = Gicv3::G1NS; 83913920Sgiacomo.travaglini@arm.com bool group_enabled = distributor->groupEnabled(lpi_group); 84013690Sjairo.balart@metempsy.com 84113920Sgiacomo.travaglini@arm.com if (lpi_is_pending && lpi_is_enable && group_enabled) { 84213921Sgiacomo.travaglini@arm.com uint8_t lpi_priority =config_entry.priority; 84313690Sjairo.balart@metempsy.com 84413920Sgiacomo.travaglini@arm.com if ((lpi_priority < cpuInterface->hppi.prio) || 84513920Sgiacomo.travaglini@arm.com (lpi_priority == cpuInterface->hppi.prio && 84613920Sgiacomo.travaglini@arm.com lpi_id < cpuInterface->hppi.intid)) { 84713920Sgiacomo.travaglini@arm.com cpuInterface->hppi.intid = lpi_id; 84813920Sgiacomo.travaglini@arm.com cpuInterface->hppi.prio = lpi_priority; 84913920Sgiacomo.travaglini@arm.com cpuInterface->hppi.group = lpi_group; 85013920Sgiacomo.travaglini@arm.com new_hppi = true; 85113920Sgiacomo.travaglini@arm.com } 85213690Sjairo.balart@metempsy.com } 85313690Sjairo.balart@metempsy.com } 85413690Sjairo.balart@metempsy.com } 85513690Sjairo.balart@metempsy.com 85613531Sjairo.balart@metempsy.com if (!new_hppi && cpuInterface->hppi.prio != 0xff && 85713756Sjairo.balart@metempsy.com cpuInterface->hppi.intid < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 85813531Sjairo.balart@metempsy.com distributor->fullUpdate(); 85913531Sjairo.balart@metempsy.com } 86013531Sjairo.balart@metempsy.com} 86113531Sjairo.balart@metempsy.com 86213531Sjairo.balart@metempsy.comvoid 86313690Sjairo.balart@metempsy.comGicv3Redistributor::setClrLPI(uint64_t data, bool set) 86413690Sjairo.balart@metempsy.com{ 86513690Sjairo.balart@metempsy.com if (!EnableLPIs) { 86613690Sjairo.balart@metempsy.com // Writes to GICR_SETLPIR or GICR_CLRLPIR have not effect if 86713690Sjairo.balart@metempsy.com // GICR_CTLR.EnableLPIs == 0. 86813690Sjairo.balart@metempsy.com return; 86913690Sjairo.balart@metempsy.com } 87013690Sjairo.balart@metempsy.com 87113690Sjairo.balart@metempsy.com uint32_t lpi_id = data & 0xffffffff; 87213917Sgiacomo.travaglini@arm.com uint32_t largest_lpi_id = 1 << (lpiIDBits + 1); 87313690Sjairo.balart@metempsy.com 87413690Sjairo.balart@metempsy.com if (lpi_id > largest_lpi_id) { 87513690Sjairo.balart@metempsy.com // Writes to GICR_SETLPIR or GICR_CLRLPIR have not effect if 87613690Sjairo.balart@metempsy.com // pINTID value specifies an unimplemented LPI. 87713690Sjairo.balart@metempsy.com return; 87813690Sjairo.balart@metempsy.com } 87913690Sjairo.balart@metempsy.com 88013690Sjairo.balart@metempsy.com Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8); 88113690Sjairo.balart@metempsy.com uint8_t lpi_pending_entry; 88213690Sjairo.balart@metempsy.com ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId); 88313919Sgiacomo.travaglini@arm.com tc->getPhysProxy().readBlob(lpi_pending_entry_ptr, 88413690Sjairo.balart@metempsy.com (uint8_t*) &lpi_pending_entry, 88513690Sjairo.balart@metempsy.com sizeof(lpi_pending_entry)); 88613690Sjairo.balart@metempsy.com uint8_t lpi_pending_entry_bit_position = lpi_id % 8; 88713690Sjairo.balart@metempsy.com bool is_set = lpi_pending_entry & (1 << lpi_pending_entry_bit_position); 88813690Sjairo.balart@metempsy.com 88913690Sjairo.balart@metempsy.com if (set) { 89013690Sjairo.balart@metempsy.com if (is_set) { 89113690Sjairo.balart@metempsy.com // Writes to GICR_SETLPIR have not effect if the pINTID field 89213690Sjairo.balart@metempsy.com // corresponds to an LPI that is already pending. 89313690Sjairo.balart@metempsy.com return; 89413690Sjairo.balart@metempsy.com } 89513690Sjairo.balart@metempsy.com 89613690Sjairo.balart@metempsy.com lpi_pending_entry |= 1 << (lpi_pending_entry_bit_position); 89713690Sjairo.balart@metempsy.com } else { 89813690Sjairo.balart@metempsy.com if (!is_set) { 89913690Sjairo.balart@metempsy.com // Writes to GICR_SETLPIR have not effect if the pINTID field 90013690Sjairo.balart@metempsy.com // corresponds to an LPI that is not pending. 90113690Sjairo.balart@metempsy.com return; 90213690Sjairo.balart@metempsy.com } 90313690Sjairo.balart@metempsy.com 90413690Sjairo.balart@metempsy.com lpi_pending_entry &= ~(1 << (lpi_pending_entry_bit_position)); 90513690Sjairo.balart@metempsy.com } 90613690Sjairo.balart@metempsy.com 90713919Sgiacomo.travaglini@arm.com tc->getPhysProxy().writeBlob(lpi_pending_entry_ptr, 90813690Sjairo.balart@metempsy.com (uint8_t*) &lpi_pending_entry, 90913690Sjairo.balart@metempsy.com sizeof(lpi_pending_entry)); 91013690Sjairo.balart@metempsy.com updateAndInformCPUInterface(); 91113690Sjairo.balart@metempsy.com} 91213690Sjairo.balart@metempsy.com 91313690Sjairo.balart@metempsy.comvoid 91413531Sjairo.balart@metempsy.comGicv3Redistributor::updateAndInformCPUInterface() 91513531Sjairo.balart@metempsy.com{ 91613531Sjairo.balart@metempsy.com update(); 91713531Sjairo.balart@metempsy.com cpuInterface->update(); 91813531Sjairo.balart@metempsy.com} 91913531Sjairo.balart@metempsy.com 92013531Sjairo.balart@metempsy.comGicv3::GroupId 92113756Sjairo.balart@metempsy.comGicv3Redistributor::getIntGroup(int int_id) const 92213531Sjairo.balart@metempsy.com{ 92313531Sjairo.balart@metempsy.com assert(int_id < (Gicv3::SGI_MAX + Gicv3::PPI_MAX)); 92413531Sjairo.balart@metempsy.com 92513531Sjairo.balart@metempsy.com if (distributor->DS) { 92613531Sjairo.balart@metempsy.com if (irqGroup[int_id] == 0) { 92713531Sjairo.balart@metempsy.com return Gicv3::G0S; 92813531Sjairo.balart@metempsy.com } else { 92913531Sjairo.balart@metempsy.com return Gicv3::G1NS; 93013531Sjairo.balart@metempsy.com } 93113531Sjairo.balart@metempsy.com } else { 93213531Sjairo.balart@metempsy.com if (irqGrpmod[int_id] == 0 && irqGroup[int_id] == 0) { 93313531Sjairo.balart@metempsy.com return Gicv3::G0S; 93413531Sjairo.balart@metempsy.com } else if (irqGrpmod[int_id] == 0 && irqGroup[int_id] == 1) { 93513531Sjairo.balart@metempsy.com return Gicv3::G1NS; 93613531Sjairo.balart@metempsy.com } else if (irqGrpmod[int_id] == 1 && irqGroup[int_id] == 0) { 93713531Sjairo.balart@metempsy.com return Gicv3::G1S; 93813531Sjairo.balart@metempsy.com } else if (irqGrpmod[int_id] == 1 && irqGroup[int_id] == 1) { 93913531Sjairo.balart@metempsy.com return Gicv3::G1NS; 94013531Sjairo.balart@metempsy.com } 94113531Sjairo.balart@metempsy.com } 94213531Sjairo.balart@metempsy.com 94313531Sjairo.balart@metempsy.com M5_UNREACHABLE; 94413531Sjairo.balart@metempsy.com} 94513531Sjairo.balart@metempsy.com 94613531Sjairo.balart@metempsy.comvoid 94713531Sjairo.balart@metempsy.comGicv3Redistributor::activateIRQ(uint32_t int_id) 94813531Sjairo.balart@metempsy.com{ 94913531Sjairo.balart@metempsy.com irqPending[int_id] = false; 95013531Sjairo.balart@metempsy.com irqActive[int_id] = true; 95113531Sjairo.balart@metempsy.com} 95213531Sjairo.balart@metempsy.com 95313531Sjairo.balart@metempsy.comvoid 95413531Sjairo.balart@metempsy.comGicv3Redistributor::deactivateIRQ(uint32_t int_id) 95513531Sjairo.balart@metempsy.com{ 95613531Sjairo.balart@metempsy.com irqActive[int_id] = false; 95713531Sjairo.balart@metempsy.com} 95813531Sjairo.balart@metempsy.com 95913531Sjairo.balart@metempsy.comuint32_t 96013756Sjairo.balart@metempsy.comGicv3Redistributor::getAffinity() const 96113531Sjairo.balart@metempsy.com{ 96213531Sjairo.balart@metempsy.com ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId); 96313531Sjairo.balart@metempsy.com uint64_t mpidr = getMPIDR(gic->getSystem(), tc); 96413531Sjairo.balart@metempsy.com /* 96513531Sjairo.balart@metempsy.com * Aff3 = MPIDR[39:32] 96613531Sjairo.balart@metempsy.com * (Note getMPIDR() returns uint32_t so Aff3 is always 0...) 96713531Sjairo.balart@metempsy.com * Aff2 = MPIDR[23:16] 96813531Sjairo.balart@metempsy.com * Aff1 = MPIDR[15:8] 96913531Sjairo.balart@metempsy.com * Aff0 = MPIDR[7:0] 97013531Sjairo.balart@metempsy.com * affinity = Aff3.Aff2.Aff1.Aff0 97113531Sjairo.balart@metempsy.com */ 97213531Sjairo.balart@metempsy.com uint64_t affinity = ((mpidr & 0xff00000000) >> 8) | (mpidr & (0xffffff)); 97313531Sjairo.balart@metempsy.com return affinity; 97413531Sjairo.balart@metempsy.com} 97513531Sjairo.balart@metempsy.com 97613531Sjairo.balart@metempsy.combool 97713756Sjairo.balart@metempsy.comGicv3Redistributor::canBeSelectedFor1toNInterrupt(Gicv3::GroupId group) const 97813531Sjairo.balart@metempsy.com{ 97913531Sjairo.balart@metempsy.com if (peInLowPowerState) { 98013531Sjairo.balart@metempsy.com return false; 98113531Sjairo.balart@metempsy.com } 98213531Sjairo.balart@metempsy.com 98313531Sjairo.balart@metempsy.com if (!distributor->groupEnabled(group)) { 98413531Sjairo.balart@metempsy.com return false; 98513531Sjairo.balart@metempsy.com } 98613531Sjairo.balart@metempsy.com 98713531Sjairo.balart@metempsy.com if ((group == Gicv3::G1S) && DPG1S) { 98813531Sjairo.balart@metempsy.com return false; 98913531Sjairo.balart@metempsy.com } 99013531Sjairo.balart@metempsy.com 99113531Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && DPG1NS) { 99213531Sjairo.balart@metempsy.com return false; 99313531Sjairo.balart@metempsy.com } 99413531Sjairo.balart@metempsy.com 99513531Sjairo.balart@metempsy.com if ((group == Gicv3::G0S) && DPG0) { 99613531Sjairo.balart@metempsy.com return false; 99713531Sjairo.balart@metempsy.com } 99813531Sjairo.balart@metempsy.com 99913531Sjairo.balart@metempsy.com return true; 100013531Sjairo.balart@metempsy.com} 100113531Sjairo.balart@metempsy.com 100213531Sjairo.balart@metempsy.comvoid 100313531Sjairo.balart@metempsy.comGicv3Redistributor::serialize(CheckpointOut & cp) const 100413531Sjairo.balart@metempsy.com{ 100513531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(peInLowPowerState); 100613531Sjairo.balart@metempsy.com SERIALIZE_CONTAINER(irqGroup); 100713531Sjairo.balart@metempsy.com SERIALIZE_CONTAINER(irqEnabled); 100813531Sjairo.balart@metempsy.com SERIALIZE_CONTAINER(irqPending); 100913531Sjairo.balart@metempsy.com SERIALIZE_CONTAINER(irqActive); 101013531Sjairo.balart@metempsy.com SERIALIZE_CONTAINER(irqPriority); 101113531Sjairo.balart@metempsy.com SERIALIZE_CONTAINER(irqConfig); 101213531Sjairo.balart@metempsy.com SERIALIZE_CONTAINER(irqGrpmod); 101313531Sjairo.balart@metempsy.com SERIALIZE_CONTAINER(irqNsacr); 101413531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(DPG1S); 101513531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(DPG1NS); 101613531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(DPG0); 101713690Sjairo.balart@metempsy.com SERIALIZE_SCALAR(EnableLPIs); 101813690Sjairo.balart@metempsy.com SERIALIZE_SCALAR(lpiConfigurationTablePtr); 101913690Sjairo.balart@metempsy.com SERIALIZE_SCALAR(lpiIDBits); 102013690Sjairo.balart@metempsy.com SERIALIZE_SCALAR(lpiPendingTablePtr); 102113531Sjairo.balart@metempsy.com} 102213531Sjairo.balart@metempsy.com 102313531Sjairo.balart@metempsy.comvoid 102413531Sjairo.balart@metempsy.comGicv3Redistributor::unserialize(CheckpointIn & cp) 102513531Sjairo.balart@metempsy.com{ 102613531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(peInLowPowerState); 102713531Sjairo.balart@metempsy.com UNSERIALIZE_CONTAINER(irqGroup); 102813531Sjairo.balart@metempsy.com UNSERIALIZE_CONTAINER(irqEnabled); 102913531Sjairo.balart@metempsy.com UNSERIALIZE_CONTAINER(irqPending); 103013531Sjairo.balart@metempsy.com UNSERIALIZE_CONTAINER(irqActive); 103113531Sjairo.balart@metempsy.com UNSERIALIZE_CONTAINER(irqPriority); 103213531Sjairo.balart@metempsy.com UNSERIALIZE_CONTAINER(irqConfig); 103313531Sjairo.balart@metempsy.com UNSERIALIZE_CONTAINER(irqGrpmod); 103413531Sjairo.balart@metempsy.com UNSERIALIZE_CONTAINER(irqNsacr); 103513531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(DPG1S); 103613531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(DPG1NS); 103713531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(DPG0); 103813690Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(EnableLPIs); 103913690Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(lpiConfigurationTablePtr); 104013690Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(lpiIDBits); 104113690Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(lpiPendingTablePtr); 104213531Sjairo.balart@metempsy.com} 1043