gic_v3_distributor.hh revision 14257:0398747c0a91
112337Sjason@lowepower.com/* 212337Sjason@lowepower.com * Copyright (c) 2019 ARM Limited 312337Sjason@lowepower.com * All rights reserved 412337Sjason@lowepower.com * 512337Sjason@lowepower.com * The license below extends only to copyright in the software and shall 612337Sjason@lowepower.com * not be construed as granting a license to any other intellectual 712337Sjason@lowepower.com * property including but not limited to intellectual property relating 812337Sjason@lowepower.com * to a hardware implementation of the functionality of the software 912337Sjason@lowepower.com * licensed hereunder. You may use the software subject to the license 1012337Sjason@lowepower.com * terms below provided that you ensure that this notice is replicated 1112337Sjason@lowepower.com * unmodified and in its entirety in all distributions of the software, 1212337Sjason@lowepower.com * modified or unmodified, in source code or in binary form. 1312337Sjason@lowepower.com * 1412337Sjason@lowepower.com * Copyright (c) 2018 Metempsy Technology Consulting 1512337Sjason@lowepower.com * All rights reserved. 1612337Sjason@lowepower.com * 1712337Sjason@lowepower.com * Redistribution and use in source and binary forms, with or without 1812337Sjason@lowepower.com * modification, are permitted provided that the following conditions are 1912337Sjason@lowepower.com * met: redistributions of source code must retain the above copyright 2012337Sjason@lowepower.com * notice, this list of conditions and the following disclaimer; 2112337Sjason@lowepower.com * redistributions in binary form must reproduce the above copyright 2212337Sjason@lowepower.com * notice, this list of conditions and the following disclaimer in the 2312337Sjason@lowepower.com * documentation and/or other materials provided with the distribution; 2412337Sjason@lowepower.com * neither the name of the copyright holders nor the names of its 2512337Sjason@lowepower.com * contributors may be used to endorse or promote products derived from 2612337Sjason@lowepower.com * this software without specific prior written permission. 2712337Sjason@lowepower.com * 2812337Sjason@lowepower.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2912337Sjason@lowepower.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3012337Sjason@lowepower.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3112337Sjason@lowepower.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3212337Sjason@lowepower.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3312337Sjason@lowepower.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3412337Sjason@lowepower.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3512337Sjason@lowepower.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3612337Sjason@lowepower.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3712337Sjason@lowepower.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3812337Sjason@lowepower.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3912337Sjason@lowepower.com * 4012337Sjason@lowepower.com * Authors: Jairo Balart 4112337Sjason@lowepower.com */ 4212337Sjason@lowepower.com 4312337Sjason@lowepower.com#ifndef __DEV_ARM_GICV3_DISTRIBUTOR_H__ 4412337Sjason@lowepower.com#define __DEV_ARM_GICV3_DISTRIBUTOR_H__ 4512337Sjason@lowepower.com 4612337Sjason@lowepower.com#include "base/addr_range.hh" 4712337Sjason@lowepower.com#include "dev/arm/gic_v3.hh" 4812337Sjason@lowepower.com#include "sim/serialize.hh" 4912337Sjason@lowepower.com 5012337Sjason@lowepower.comclass Gicv3Distributor : public Serializable 5112337Sjason@lowepower.com{ 5212337Sjason@lowepower.com private: 5312337Sjason@lowepower.com 5412337Sjason@lowepower.com friend class Gicv3Redistributor; 5512337Sjason@lowepower.com friend class Gicv3CPUInterface; 5612337Sjason@lowepower.com friend class Gicv3Its; 5712337Sjason@lowepower.com 5812337Sjason@lowepower.com protected: 5912337Sjason@lowepower.com 6012337Sjason@lowepower.com Gicv3 * gic; 6112337Sjason@lowepower.com const uint32_t itLines; 6212337Sjason@lowepower.com 6312337Sjason@lowepower.com enum { 6412337Sjason@lowepower.com // Control Register 6512337Sjason@lowepower.com GICD_CTLR = 0x0000, 6612337Sjason@lowepower.com // Interrupt Controller Type Register 6712337Sjason@lowepower.com GICD_TYPER = 0x0004, 6812337Sjason@lowepower.com // Implementer Identification Register 6912337Sjason@lowepower.com GICD_IIDR = 0x0008, 7012337Sjason@lowepower.com // Error Reporting Status Register 7112337Sjason@lowepower.com GICD_STATUSR = 0x0010, 7212337Sjason@lowepower.com // Set Non-secure SPI Pending Register 7312337Sjason@lowepower.com GICD_SETSPI_NSR = 0x0040, 7412337Sjason@lowepower.com // Clear Non-secure SPI Pending Register 7512337Sjason@lowepower.com GICD_CLRSPI_NSR = 0x0048, 7612337Sjason@lowepower.com // Set Secure SPI Pending Register 7712337Sjason@lowepower.com GICD_SETSPI_SR = 0x0050, 7812337Sjason@lowepower.com // Clear Secure SPI Pending Register 7912337Sjason@lowepower.com GICD_CLRSPI_SR = 0x0058, 8012337Sjason@lowepower.com // Software Generated Interrupt Register 8112337Sjason@lowepower.com GICD_SGIR = 0x0f00, 8212337Sjason@lowepower.com // Peripheral ID0 Register 8312337Sjason@lowepower.com GICD_PIDR0 = 0xffe0, 8412337Sjason@lowepower.com // Peripheral ID1 Register 8512337Sjason@lowepower.com GICD_PIDR1 = 0xffe4, 8612337Sjason@lowepower.com // Peripheral ID2 Register 8712337Sjason@lowepower.com GICD_PIDR2 = 0xffe8, 8812337Sjason@lowepower.com // Peripheral ID3 Register 8912337Sjason@lowepower.com GICD_PIDR3 = 0xffec, 9012337Sjason@lowepower.com // Peripheral ID4 Register 9112337Sjason@lowepower.com GICD_PIDR4 = 0xffd0, 9212337Sjason@lowepower.com // Peripheral ID5 Register 9312337Sjason@lowepower.com GICD_PIDR5 = 0xffd4, 9412337Sjason@lowepower.com // Peripheral ID6 Register 9512337Sjason@lowepower.com GICD_PIDR6 = 0xffd8, 9612337Sjason@lowepower.com // Peripheral ID7 Register 9712337Sjason@lowepower.com GICD_PIDR7 = 0xffdc, 9812337Sjason@lowepower.com }; 9912337Sjason@lowepower.com 10012337Sjason@lowepower.com // Interrupt Group Registers 10112337Sjason@lowepower.com static const AddrRange GICD_IGROUPR; 10212337Sjason@lowepower.com // Interrupt Set-Enable Registers 10312337Sjason@lowepower.com static const AddrRange GICD_ISENABLER; 104 // Interrupt Clear-Enable Registers 105 static const AddrRange GICD_ICENABLER; 106 // Interrupt Set-Pending Registers 107 static const AddrRange GICD_ISPENDR; 108 // Interrupt Clear-Pending Registers 109 static const AddrRange GICD_ICPENDR; 110 // Interrupt Set-Active Registers 111 static const AddrRange GICD_ISACTIVER; 112 // Interrupt Clear-Active Registers 113 static const AddrRange GICD_ICACTIVER; 114 // Interrupt Priority Registers 115 static const AddrRange GICD_IPRIORITYR; 116 // Interrupt Processor Targets Registers 117 static const AddrRange GICD_ITARGETSR; // GICv2 legacy 118 // Interrupt Configuration Registers 119 static const AddrRange GICD_ICFGR; 120 // Interrupt Group Modifier Registers 121 static const AddrRange GICD_IGRPMODR; 122 // Non-secure Access Control Registers 123 static const AddrRange GICD_NSACR; 124 // SGI Clear-Pending Registers 125 static const AddrRange GICD_CPENDSGIR; // GICv2 legacy 126 // SGI Set-Pending Registers 127 static const AddrRange GICD_SPENDSGIR; // GICv2 legacy 128 // Interrupt Routing Registers 129 static const AddrRange GICD_IROUTER; 130 131 BitUnion64(IROUTER) 132 Bitfield<63, 40> res0_1; 133 Bitfield<39, 32> Aff3; 134 Bitfield<31> IRM; 135 Bitfield<30, 24> res0_2; 136 Bitfield<23, 16> Aff2; 137 Bitfield<15, 8> Aff1; 138 Bitfield<7, 0> Aff0; 139 EndBitUnion(IROUTER) 140 141 static const uint32_t GICD_CTLR_ENABLEGRP0 = 1 << 0; 142 static const uint32_t GICD_CTLR_ENABLEGRP1 = 1 << 0; 143 static const uint32_t GICD_CTLR_ENABLEGRP1NS = 1 << 1; 144 static const uint32_t GICD_CTLR_ENABLEGRP1A = 1 << 1; 145 static const uint32_t GICD_CTLR_ENABLEGRP1S = 1 << 2; 146 static const uint32_t GICD_CTLR_DS = 1 << 6; 147 148 bool ARE; 149 bool DS; 150 bool EnableGrp1S; 151 bool EnableGrp1NS; 152 bool EnableGrp0; 153 std::vector <uint8_t> irqGroup; 154 std::vector <bool> irqEnabled; 155 std::vector <bool> irqPending; 156 std::vector <bool> irqActive; 157 std::vector <uint8_t> irqPriority; 158 std::vector <Gicv3::IntTriggerType> irqConfig; 159 std::vector <uint8_t> irqGrpmod; 160 std::vector <uint8_t> irqNsacr; 161 std::vector <IROUTER> irqAffinityRouting; 162 163 uint32_t gicdTyper; 164 uint32_t gicdPidr0; 165 uint32_t gicdPidr1; 166 uint32_t gicdPidr2; 167 uint32_t gicdPidr3; 168 uint32_t gicdPidr4; 169 170 public: 171 172 static const uint32_t ADDR_RANGE_SIZE = 0x10000; 173 static const uint32_t IDBITS = 0xf; 174 175 protected: 176 177 void activateIRQ(uint32_t int_id); 178 void deactivateIRQ(uint32_t int_id); 179 void fullUpdate(); 180 Gicv3::GroupId getIntGroup(int int_id) const; 181 182 inline bool 183 groupEnabled(Gicv3::GroupId group) const 184 { 185 if (DS == 0) { 186 switch (group) { 187 case Gicv3::G0S: 188 return EnableGrp0; 189 190 case Gicv3::G1S: 191 return EnableGrp1S; 192 193 case Gicv3::G1NS: 194 return EnableGrp1NS; 195 196 default: 197 panic("Gicv3Distributor::groupEnabled(): " 198 "invalid group!\n"); 199 } 200 } else { 201 switch (group) { 202 case Gicv3::G0S: 203 return EnableGrp0; 204 205 case Gicv3::G1S: 206 case Gicv3::G1NS: 207 return EnableGrp1NS; 208 209 default: 210 panic("Gicv3Distributor::groupEnabled(): " 211 "invalid group!\n"); 212 } 213 } 214 } 215 216 Gicv3::IntStatus intStatus(uint32_t int_id) const; 217 218 inline bool isNotSPI(uint32_t int_id) const 219 { 220 if (int_id < (Gicv3::SGI_MAX + Gicv3::PPI_MAX) || int_id >= itLines) { 221 return true; 222 } else { 223 return false; 224 } 225 } 226 227 inline bool nsAccessToSecInt(uint32_t int_id, bool is_secure_access) const 228 { 229 return !DS && !is_secure_access && getIntGroup(int_id) != Gicv3::G1NS; 230 } 231 232 void reset(); 233 void serialize(CheckpointOut & cp) const override; 234 void unserialize(CheckpointIn & cp) override; 235 void update(); 236 Gicv3CPUInterface* route(uint32_t int_id); 237 238 public: 239 240 Gicv3Distributor(Gicv3 * gic, uint32_t it_lines); 241 242 void deassertSPI(uint32_t int_id); 243 void clearIrqCpuInterface(uint32_t int_id); 244 void init(); 245 void initState(); 246 uint64_t read(Addr addr, size_t size, bool is_secure_access); 247 void sendInt(uint32_t int_id); 248 void write(Addr addr, uint64_t data, size_t size, 249 bool is_secure_access); 250}; 251 252#endif //__DEV_ARM_GICV3_DISTRIBUTOR_H__ 253