gic_v3_distributor.hh revision 14251:44fa3373ab0b 
1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2018 Metempsy Technology Consulting
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Jairo Balart
41 */
42
43#ifndef __DEV_ARM_GICV3_DISTRIBUTOR_H__
44#define __DEV_ARM_GICV3_DISTRIBUTOR_H__
45
46#include "base/addr_range.hh"
47#include "dev/arm/gic_v3.hh"
48#include "sim/serialize.hh"
49
50class Gicv3Distributor : public Serializable
51{
52  private:
53
54    friend class Gicv3Redistributor;
55    friend class Gicv3CPUInterface;
56    friend class Gicv3Its;
57
58  protected:
59
60    Gicv3 * gic;
61    const uint32_t itLines;
62
63    enum {
64        // Control Register
65        GICD_CTLR  = 0x0000,
66        // Interrupt Controller Type Register
67        GICD_TYPER = 0x0004,
68        // Implementer Identification Register
69        GICD_IIDR = 0x0008,
70        // Error Reporting Status Register
71        GICD_STATUSR = 0x0010,
72        // Software Generated Interrupt Register
73        GICD_SGIR = 0x0f00,
74        // Peripheral ID0 Register
75        GICD_PIDR0 = 0xffe0,
76        // Peripheral ID1 Register
77        GICD_PIDR1 = 0xffe4,
78        // Peripheral ID2 Register
79        GICD_PIDR2 = 0xffe8,
80        // Peripheral ID3 Register
81        GICD_PIDR3 = 0xffec,
82        // Peripheral ID4 Register
83        GICD_PIDR4 = 0xffd0,
84        // Peripheral ID5 Register
85        GICD_PIDR5 = 0xffd4,
86        // Peripheral ID6 Register
87        GICD_PIDR6 = 0xffd8,
88        // Peripheral ID7 Register
89        GICD_PIDR7 = 0xffdc,
90    };
91
92    // Interrupt Group Registers
93    static const AddrRange GICD_IGROUPR;
94    // Interrupt Set-Enable Registers
95    static const AddrRange GICD_ISENABLER;
96    // Interrupt Clear-Enable Registers
97    static const AddrRange GICD_ICENABLER;
98    // Interrupt Set-Pending Registers
99    static const AddrRange GICD_ISPENDR;
100    // Interrupt Clear-Pending Registers
101    static const AddrRange GICD_ICPENDR;
102    // Interrupt Set-Active Registers
103    static const AddrRange GICD_ISACTIVER;
104    // Interrupt Clear-Active Registers
105    static const AddrRange GICD_ICACTIVER;
106    // Interrupt Priority Registers
107    static const AddrRange GICD_IPRIORITYR;
108    // Interrupt Processor Targets Registers
109    static const AddrRange GICD_ITARGETSR; // GICv2 legacy
110    // Interrupt Configuration Registers
111    static const AddrRange GICD_ICFGR;
112    // Interrupt Group Modifier Registers
113    static const AddrRange GICD_IGRPMODR;
114    // Non-secure Access Control Registers
115    static const AddrRange GICD_NSACR;
116    // SGI Clear-Pending Registers
117    static const AddrRange GICD_CPENDSGIR; // GICv2 legacy
118    // SGI Set-Pending Registers
119    static const AddrRange GICD_SPENDSGIR; // GICv2 legacy
120    // Interrupt Routing Registers
121    static const AddrRange GICD_IROUTER;
122
123    BitUnion64(IROUTER)
124        Bitfield<63, 40> res0_1;
125        Bitfield<39, 32> Aff3;
126        Bitfield<31>     IRM;
127        Bitfield<30, 24> res0_2;
128        Bitfield<23, 16> Aff2;
129        Bitfield<15, 8>  Aff1;
130        Bitfield<7, 0>   Aff0;
131    EndBitUnion(IROUTER)
132
133    static const uint32_t GICD_CTLR_ENABLEGRP0   = 1 << 0;
134    static const uint32_t GICD_CTLR_ENABLEGRP1   = 1 << 0;
135    static const uint32_t GICD_CTLR_ENABLEGRP1NS = 1 << 1;
136    static const uint32_t GICD_CTLR_ENABLEGRP1A  = 1 << 1;
137    static const uint32_t GICD_CTLR_ENABLEGRP1S  = 1 << 2;
138    static const uint32_t GICD_CTLR_DS           = 1 << 6;
139
140    bool ARE;
141    bool DS;
142    bool EnableGrp1S;
143    bool EnableGrp1NS;
144    bool EnableGrp0;
145    std::vector <uint8_t> irqGroup;
146    std::vector <bool> irqEnabled;
147    std::vector <bool> irqPending;
148    std::vector <bool> irqActive;
149    std::vector <uint8_t> irqPriority;
150    std::vector <Gicv3::IntTriggerType> irqConfig;
151    std::vector <uint8_t> irqGrpmod;
152    std::vector <uint8_t> irqNsacr;
153    std::vector <IROUTER> irqAffinityRouting;
154
155    uint32_t gicdPidr0;
156    uint32_t gicdPidr1;
157    uint32_t gicdPidr2;
158    uint32_t gicdPidr3;
159    uint32_t gicdPidr4;
160
161  public:
162
163    static const uint32_t ADDR_RANGE_SIZE = 0x10000;
164    static const uint32_t IDBITS = 0xf;
165
166  protected:
167
168    void activateIRQ(uint32_t int_id);
169    void deactivateIRQ(uint32_t int_id);
170    void fullUpdate();
171    Gicv3::GroupId getIntGroup(int int_id) const;
172
173    inline bool
174    groupEnabled(Gicv3::GroupId group) const
175    {
176        if (DS == 0) {
177            switch (group) {
178              case Gicv3::G0S:
179                return EnableGrp0;
180
181              case Gicv3::G1S:
182                return EnableGrp1S;
183
184              case Gicv3::G1NS:
185                return EnableGrp1NS;
186
187              default:
188                panic("Gicv3Distributor::groupEnabled(): "
189                        "invalid group!\n");
190            }
191        } else {
192            switch (group) {
193              case Gicv3::G0S:
194                return EnableGrp0;
195
196              case Gicv3::G1S:
197              case Gicv3::G1NS:
198                return EnableGrp1NS;
199
200              default:
201                panic("Gicv3Distributor::groupEnabled(): "
202                        "invalid group!\n");
203            }
204        }
205    }
206
207    Gicv3::IntStatus intStatus(uint32_t int_id) const;
208
209    inline bool isNotSPI(uint32_t int_id) const
210    {
211        if (int_id < (Gicv3::SGI_MAX + Gicv3::PPI_MAX) || int_id >= itLines) {
212            return true;
213        } else {
214            return false;
215        }
216    }
217
218    inline bool nsAccessToSecInt(uint32_t int_id, bool is_secure_access) const
219    {
220        return !DS && !is_secure_access && getIntGroup(int_id) != Gicv3::G1NS;
221    }
222
223    void reset();
224    void serialize(CheckpointOut & cp) const override;
225    void unserialize(CheckpointIn & cp) override;
226    void update();
227    Gicv3CPUInterface* route(uint32_t int_id);
228
229  public:
230
231    Gicv3Distributor(Gicv3 * gic, uint32_t it_lines);
232
233    void deassertSPI(uint32_t int_id);
234    void clearIrqCpuInterface(uint32_t int_id);
235    void init();
236    void initState();
237    uint64_t read(Addr addr, size_t size, bool is_secure_access);
238    void sendInt(uint32_t int_id);
239    void write(Addr addr, uint64_t data, size_t size,
240               bool is_secure_access);
241};
242
243#endif //__DEV_ARM_GICV3_DISTRIBUTOR_H__
244