gic_v3_distributor.hh revision 14251
16313Sgblack@eecs.umich.edu/* 26313Sgblack@eecs.umich.edu * Copyright (c) 2019 ARM Limited 36313Sgblack@eecs.umich.edu * All rights reserved 46313Sgblack@eecs.umich.edu * 56313Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 66313Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 76313Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 86313Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 96313Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 106313Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 116313Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 126313Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 136313Sgblack@eecs.umich.edu * 146313Sgblack@eecs.umich.edu * Copyright (c) 2018 Metempsy Technology Consulting 156313Sgblack@eecs.umich.edu * All rights reserved. 166313Sgblack@eecs.umich.edu * 176313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266313Sgblack@eecs.umich.edu * this software without specific prior written permission. 276313Sgblack@eecs.umich.edu * 286313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 348229Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356334Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366334Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376334Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386334Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396313Sgblack@eecs.umich.edu * 406334Sgblack@eecs.umich.edu * Authors: Jairo Balart 419384SAndreas.Sandberg@arm.com */ 426313Sgblack@eecs.umich.edu 436334Sgblack@eecs.umich.edu#ifndef __DEV_ARM_GICV3_DISTRIBUTOR_H__ 446313Sgblack@eecs.umich.edu#define __DEV_ARM_GICV3_DISTRIBUTOR_H__ 456313Sgblack@eecs.umich.edu 469384SAndreas.Sandberg@arm.com#include "base/addr_range.hh" 476334Sgblack@eecs.umich.edu#include "dev/arm/gic_v3.hh" 486313Sgblack@eecs.umich.edu#include "sim/serialize.hh" 496313Sgblack@eecs.umich.edu 506313Sgblack@eecs.umich.educlass Gicv3Distributor : public Serializable 519384SAndreas.Sandberg@arm.com{ 526313Sgblack@eecs.umich.edu private: 536334Sgblack@eecs.umich.edu 546334Sgblack@eecs.umich.edu friend class Gicv3Redistributor; 556334Sgblack@eecs.umich.edu friend class Gicv3CPUInterface; 566334Sgblack@eecs.umich.edu friend class Gicv3Its; 579384SAndreas.Sandberg@arm.com 589384SAndreas.Sandberg@arm.com protected: 596313Sgblack@eecs.umich.edu 608181Sksewell@umich.edu Gicv3 * gic; 618181Sksewell@umich.edu const uint32_t itLines; 628181Sksewell@umich.edu 638181Sksewell@umich.edu enum { 646334Sgblack@eecs.umich.edu // Control Register 656334Sgblack@eecs.umich.edu GICD_CTLR = 0x0000, 666334Sgblack@eecs.umich.edu // Interrupt Controller Type Register 676334Sgblack@eecs.umich.edu GICD_TYPER = 0x0004, 686334Sgblack@eecs.umich.edu // Implementer Identification Register 696334Sgblack@eecs.umich.edu GICD_IIDR = 0x0008, 706334Sgblack@eecs.umich.edu // Error Reporting Status Register 716334Sgblack@eecs.umich.edu GICD_STATUSR = 0x0010, 726334Sgblack@eecs.umich.edu // Software Generated Interrupt Register 736334Sgblack@eecs.umich.edu GICD_SGIR = 0x0f00, 746313Sgblack@eecs.umich.edu // Peripheral ID0 Register 758181Sksewell@umich.edu GICD_PIDR0 = 0xffe0, 766334Sgblack@eecs.umich.edu // Peripheral ID1 Register 778181Sksewell@umich.edu GICD_PIDR1 = 0xffe4, 786334Sgblack@eecs.umich.edu // Peripheral ID2 Register 7910698Sandreas.hansson@arm.com GICD_PIDR2 = 0xffe8, 806334Sgblack@eecs.umich.edu // Peripheral ID3 Register 816334Sgblack@eecs.umich.edu GICD_PIDR3 = 0xffec, 826334Sgblack@eecs.umich.edu // Peripheral ID4 Register 836334Sgblack@eecs.umich.edu GICD_PIDR4 = 0xffd0, 846334Sgblack@eecs.umich.edu // Peripheral ID5 Register 856334Sgblack@eecs.umich.edu GICD_PIDR5 = 0xffd4, 866334Sgblack@eecs.umich.edu // Peripheral ID6 Register 876334Sgblack@eecs.umich.edu GICD_PIDR6 = 0xffd8, 886334Sgblack@eecs.umich.edu // Peripheral ID7 Register 896334Sgblack@eecs.umich.edu GICD_PIDR7 = 0xffdc, 9010698Sandreas.hansson@arm.com }; 916334Sgblack@eecs.umich.edu 926334Sgblack@eecs.umich.edu // Interrupt Group Registers 936334Sgblack@eecs.umich.edu static const AddrRange GICD_IGROUPR; 946334Sgblack@eecs.umich.edu // Interrupt Set-Enable Registers 956334Sgblack@eecs.umich.edu static const AddrRange GICD_ISENABLER; 966334Sgblack@eecs.umich.edu // Interrupt Clear-Enable Registers 976334Sgblack@eecs.umich.edu static const AddrRange GICD_ICENABLER; 986334Sgblack@eecs.umich.edu // Interrupt Set-Pending Registers 996334Sgblack@eecs.umich.edu static const AddrRange GICD_ISPENDR; 1006334Sgblack@eecs.umich.edu // Interrupt Clear-Pending Registers 1016334Sgblack@eecs.umich.edu static const AddrRange GICD_ICPENDR; 1026334Sgblack@eecs.umich.edu // Interrupt Set-Active Registers 1036334Sgblack@eecs.umich.edu static const AddrRange GICD_ISACTIVER; 1046334Sgblack@eecs.umich.edu // Interrupt Clear-Active Registers 1056334Sgblack@eecs.umich.edu static const AddrRange GICD_ICACTIVER; 1066334Sgblack@eecs.umich.edu // Interrupt Priority Registers 1076334Sgblack@eecs.umich.edu static const AddrRange GICD_IPRIORITYR; 1086334Sgblack@eecs.umich.edu // Interrupt Processor Targets Registers 1096334Sgblack@eecs.umich.edu static const AddrRange GICD_ITARGETSR; // GICv2 legacy 1106334Sgblack@eecs.umich.edu // Interrupt Configuration Registers 1116334Sgblack@eecs.umich.edu static const AddrRange GICD_ICFGR; 1126334Sgblack@eecs.umich.edu // Interrupt Group Modifier Registers 1136334Sgblack@eecs.umich.edu static const AddrRange GICD_IGRPMODR; 1146334Sgblack@eecs.umich.edu // Non-secure Access Control Registers 1156334Sgblack@eecs.umich.edu static const AddrRange GICD_NSACR; 1166334Sgblack@eecs.umich.edu // SGI Clear-Pending Registers 1176334Sgblack@eecs.umich.edu static const AddrRange GICD_CPENDSGIR; // GICv2 legacy 1186334Sgblack@eecs.umich.edu // SGI Set-Pending Registers 1196334Sgblack@eecs.umich.edu static const AddrRange GICD_SPENDSGIR; // GICv2 legacy 1206334Sgblack@eecs.umich.edu // Interrupt Routing Registers 1216334Sgblack@eecs.umich.edu static const AddrRange GICD_IROUTER; 1226313Sgblack@eecs.umich.edu 1236334Sgblack@eecs.umich.edu BitUnion64(IROUTER) 1246334Sgblack@eecs.umich.edu Bitfield<63, 40> res0_1; 1256334Sgblack@eecs.umich.edu Bitfield<39, 32> Aff3; 1266334Sgblack@eecs.umich.edu Bitfield<31> IRM; 1276334Sgblack@eecs.umich.edu Bitfield<30, 24> res0_2; 1286313Sgblack@eecs.umich.edu Bitfield<23, 16> Aff2; 1296334Sgblack@eecs.umich.edu Bitfield<15, 8> Aff1; 1306334Sgblack@eecs.umich.edu Bitfield<7, 0> Aff0; 1316334Sgblack@eecs.umich.edu EndBitUnion(IROUTER) 1326313Sgblack@eecs.umich.edu 1336334Sgblack@eecs.umich.edu static const uint32_t GICD_CTLR_ENABLEGRP0 = 1 << 0; 1346334Sgblack@eecs.umich.edu static const uint32_t GICD_CTLR_ENABLEGRP1 = 1 << 0; 1356313Sgblack@eecs.umich.edu static const uint32_t GICD_CTLR_ENABLEGRP1NS = 1 << 1; 1366334Sgblack@eecs.umich.edu static const uint32_t GICD_CTLR_ENABLEGRP1A = 1 << 1; 1376334Sgblack@eecs.umich.edu static const uint32_t GICD_CTLR_ENABLEGRP1S = 1 << 2; 1386334Sgblack@eecs.umich.edu static const uint32_t GICD_CTLR_DS = 1 << 6; 1396334Sgblack@eecs.umich.edu 1409180Sandreas.hansson@arm.com bool ARE; 1416334Sgblack@eecs.umich.edu bool DS; 1426334Sgblack@eecs.umich.edu bool EnableGrp1S; 1436334Sgblack@eecs.umich.edu bool EnableGrp1NS; 1446334Sgblack@eecs.umich.edu bool EnableGrp0; 1456334Sgblack@eecs.umich.edu std::vector <uint8_t> irqGroup; 1466334Sgblack@eecs.umich.edu std::vector <bool> irqEnabled; 1479180Sandreas.hansson@arm.com std::vector <bool> irqPending; 1486334Sgblack@eecs.umich.edu std::vector <bool> irqActive; 1496334Sgblack@eecs.umich.edu std::vector <uint8_t> irqPriority; 1506334Sgblack@eecs.umich.edu std::vector <Gicv3::IntTriggerType> irqConfig; 1516806Sgblack@eecs.umich.edu std::vector <uint8_t> irqGrpmod; 1526334Sgblack@eecs.umich.edu std::vector <uint8_t> irqNsacr; 1536334Sgblack@eecs.umich.edu std::vector <IROUTER> irqAffinityRouting; 1546334Sgblack@eecs.umich.edu 1556334Sgblack@eecs.umich.edu uint32_t gicdPidr0; 1566334Sgblack@eecs.umich.edu uint32_t gicdPidr1; 1576334Sgblack@eecs.umich.edu uint32_t gicdPidr2; 1586334Sgblack@eecs.umich.edu uint32_t gicdPidr3; 1599461Snilay@cs.wisc.edu uint32_t gicdPidr4; 1609461Snilay@cs.wisc.edu 1619553Sandreas.hansson@arm.com public: 1629553Sandreas.hansson@arm.com 1639553Sandreas.hansson@arm.com static const uint32_t ADDR_RANGE_SIZE = 0x10000; 1649384SAndreas.Sandberg@arm.com static const uint32_t IDBITS = 0xf; 1659384SAndreas.Sandberg@arm.com 1669384SAndreas.Sandberg@arm.com protected: 1676313Sgblack@eecs.umich.edu 1686313Sgblack@eecs.umich.edu void activateIRQ(uint32_t int_id); 16910035Sandreas.hansson@arm.com void deactivateIRQ(uint32_t int_id); 1706313Sgblack@eecs.umich.edu void fullUpdate(); 1716313Sgblack@eecs.umich.edu Gicv3::GroupId getIntGroup(int int_id) const; 1726313Sgblack@eecs.umich.edu 1736313Sgblack@eecs.umich.edu inline bool 1746313Sgblack@eecs.umich.edu groupEnabled(Gicv3::GroupId group) const 17510035Sandreas.hansson@arm.com { 1766313Sgblack@eecs.umich.edu if (DS == 0) { 1776313Sgblack@eecs.umich.edu switch (group) { 1786313Sgblack@eecs.umich.edu case Gicv3::G0S: 1799920Syasuko.eckert@amd.com return EnableGrp0; 1809920Syasuko.eckert@amd.com 1819920Syasuko.eckert@amd.com case Gicv3::G1S: 18210035Sandreas.hansson@arm.com return EnableGrp1S; 1839920Syasuko.eckert@amd.com 1849920Syasuko.eckert@amd.com case Gicv3::G1NS: 1859920Syasuko.eckert@amd.com return EnableGrp1NS; 18610033SAli.Saidi@ARM.com 18710033SAli.Saidi@ARM.com default: 18810035Sandreas.hansson@arm.com panic("Gicv3Distributor::groupEnabled(): " 18910033SAli.Saidi@ARM.com "invalid group!\n"); 19010033SAli.Saidi@ARM.com } 19110033SAli.Saidi@ARM.com } else { 19210033SAli.Saidi@ARM.com switch (group) { 1936313Sgblack@eecs.umich.edu case Gicv3::G0S: 1946313Sgblack@eecs.umich.edu return EnableGrp0; 1956313Sgblack@eecs.umich.edu 1966313Sgblack@eecs.umich.edu case Gicv3::G1S: 197 case Gicv3::G1NS: 198 return EnableGrp1NS; 199 200 default: 201 panic("Gicv3Distributor::groupEnabled(): " 202 "invalid group!\n"); 203 } 204 } 205 } 206 207 Gicv3::IntStatus intStatus(uint32_t int_id) const; 208 209 inline bool isNotSPI(uint32_t int_id) const 210 { 211 if (int_id < (Gicv3::SGI_MAX + Gicv3::PPI_MAX) || int_id >= itLines) { 212 return true; 213 } else { 214 return false; 215 } 216 } 217 218 inline bool nsAccessToSecInt(uint32_t int_id, bool is_secure_access) const 219 { 220 return !DS && !is_secure_access && getIntGroup(int_id) != Gicv3::G1NS; 221 } 222 223 void reset(); 224 void serialize(CheckpointOut & cp) const override; 225 void unserialize(CheckpointIn & cp) override; 226 void update(); 227 Gicv3CPUInterface* route(uint32_t int_id); 228 229 public: 230 231 Gicv3Distributor(Gicv3 * gic, uint32_t it_lines); 232 233 void deassertSPI(uint32_t int_id); 234 void clearIrqCpuInterface(uint32_t int_id); 235 void init(); 236 void initState(); 237 uint64_t read(Addr addr, size_t size, bool is_secure_access); 238 void sendInt(uint32_t int_id); 239 void write(Addr addr, uint64_t data, size_t size, 240 bool is_secure_access); 241}; 242 243#endif //__DEV_ARM_GICV3_DISTRIBUTOR_H__ 244