gic_v3_distributor.hh revision 14167 
1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2018 Metempsy Technology Consulting
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Jairo Balart
41 */
42
43#ifndef __DEV_ARM_GICV3_DISTRIBUTOR_H__
44#define __DEV_ARM_GICV3_DISTRIBUTOR_H__
45
46#include "base/addr_range.hh"
47#include "dev/arm/gic_v3.hh"
48#include "sim/serialize.hh"
49
50class Gicv3Distributor : public Serializable
51{
52  private:
53
54    friend class Gicv3Redistributor;
55    friend class Gicv3CPUInterface;
56
57  protected:
58
59    Gicv3 * gic;
60    const uint32_t itLines;
61
62    enum {
63        // Control Register
64        GICD_CTLR  = 0x0000,
65        // Interrupt Controller Type Register
66        GICD_TYPER = 0x0004,
67        // Implementer Identification Register
68        GICD_IIDR = 0x0008,
69        // Error Reporting Status Register
70        GICD_STATUSR = 0x0010,
71        // Peripheral ID0 Register
72        GICD_PIDR0 = 0xffe0,
73        // Peripheral ID1 Register
74        GICD_PIDR1 = 0xffe4,
75        // Peripheral ID2 Register
76        GICD_PIDR2 = 0xffe8,
77        // Peripheral ID3 Register
78        GICD_PIDR3 = 0xffec,
79        // Peripheral ID4 Register
80        GICD_PIDR4 = 0xffd0,
81        // Peripheral ID5 Register
82        GICD_PIDR5 = 0xffd4,
83        // Peripheral ID6 Register
84        GICD_PIDR6 = 0xffd8,
85        // Peripheral ID7 Register
86        GICD_PIDR7 = 0xffdc,
87    };
88
89    // Interrupt Group Registers
90    static const AddrRange GICD_IGROUPR;
91    // Interrupt Set-Enable Registers
92    static const AddrRange GICD_ISENABLER;
93    // Interrupt Clear-Enable Registers
94    static const AddrRange GICD_ICENABLER;
95    // Interrupt Set-Pending Registers
96    static const AddrRange GICD_ISPENDR;
97    // Interrupt Clear-Pending Registers
98    static const AddrRange GICD_ICPENDR;
99    // Interrupt Set-Active Registers
100    static const AddrRange GICD_ISACTIVER;
101    // Interrupt Clear-Active Registers
102    static const AddrRange GICD_ICACTIVER;
103    // Interrupt Priority Registers
104    static const AddrRange GICD_IPRIORITYR;
105    // Interrupt Processor Targets Registers
106    static const AddrRange GICD_ITARGETSR; // GICv2 legacy
107    // Interrupt Configuration Registers
108    static const AddrRange GICD_ICFGR;
109    // Interrupt Group Modifier Registers
110    static const AddrRange GICD_IGRPMODR;
111    // Non-secure Access Control Registers
112    static const AddrRange GICD_NSACR;
113    // SGI Clear-Pending Registers
114    static const AddrRange GICD_CPENDSGIR; // GICv2 legacy
115    // SGI Set-Pending Registers
116    static const AddrRange GICD_SPENDSGIR; // GICv2 legacy
117    // Interrupt Routing Registers
118    static const AddrRange GICD_IROUTER;
119
120    BitUnion64(IROUTER)
121        Bitfield<63, 40> res0_1;
122        Bitfield<39, 32> Aff3;
123        Bitfield<31>     IRM;
124        Bitfield<30, 24> res0_2;
125        Bitfield<23, 16> Aff2;
126        Bitfield<15, 8>  Aff1;
127        Bitfield<7, 0>   Aff0;
128    EndBitUnion(IROUTER)
129
130    static const uint32_t GICD_CTLR_ENABLEGRP0   = 1 << 0;
131    static const uint32_t GICD_CTLR_ENABLEGRP1   = 1 << 0;
132    static const uint32_t GICD_CTLR_ENABLEGRP1NS = 1 << 1;
133    static const uint32_t GICD_CTLR_ENABLEGRP1A  = 1 << 1;
134    static const uint32_t GICD_CTLR_ENABLEGRP1S  = 1 << 2;
135    static const uint32_t GICD_CTLR_DS           = 1 << 6;
136
137    bool ARE;
138    bool DS;
139    bool EnableGrp1S;
140    bool EnableGrp1NS;
141    bool EnableGrp0;
142    std::vector <uint8_t> irqGroup;
143    std::vector <bool> irqEnabled;
144    std::vector <bool> irqPending;
145    std::vector <bool> irqActive;
146    std::vector <uint8_t> irqPriority;
147    std::vector <Gicv3::IntTriggerType> irqConfig;
148    std::vector <uint8_t> irqGrpmod;
149    std::vector <uint8_t> irqNsacr;
150    std::vector <IROUTER> irqAffinityRouting;
151
152    uint32_t gicdPidr0;
153    uint32_t gicdPidr1;
154    uint32_t gicdPidr2;
155    uint32_t gicdPidr3;
156    uint32_t gicdPidr4;
157
158  public:
159
160    static const uint32_t ADDR_RANGE_SIZE = 0x10000;
161    static const uint32_t IDBITS = 0xf;
162
163  protected:
164
165    void activateIRQ(uint32_t int_id);
166    void deactivateIRQ(uint32_t int_id);
167    void fullUpdate();
168    Gicv3::GroupId getIntGroup(int int_id) const;
169
170    inline bool
171    groupEnabled(Gicv3::GroupId group) const
172    {
173        if (DS == 0) {
174            switch (group) {
175              case Gicv3::G0S:
176                return EnableGrp0;
177
178              case Gicv3::G1S:
179                return EnableGrp1S;
180
181              case Gicv3::G1NS:
182                return EnableGrp1NS;
183
184              default:
185                panic("Gicv3Distributor::groupEnabled(): "
186                        "invalid group!\n");
187            }
188        } else {
189            switch (group) {
190              case Gicv3::G0S:
191                return EnableGrp0;
192
193              case Gicv3::G1S:
194              case Gicv3::G1NS:
195                return EnableGrp1NS;
196
197              default:
198                panic("Gicv3Distributor::groupEnabled(): "
199                        "invalid group!\n");
200            }
201        }
202    }
203
204    Gicv3::IntStatus intStatus(uint32_t int_id) const;
205
206    inline bool isNotSPI(uint32_t int_id) const
207    {
208        if (int_id < (Gicv3::SGI_MAX + Gicv3::PPI_MAX) || int_id >= itLines) {
209            return true;
210        } else {
211            return false;
212        }
213    }
214
215    inline bool nsAccessToSecInt(uint32_t int_id, bool is_secure_access) const
216    {
217        return !DS && !is_secure_access && getIntGroup(int_id) != Gicv3::G1NS;
218    }
219
220    void reset();
221    void serialize(CheckpointOut & cp) const override;
222    void unserialize(CheckpointIn & cp) override;
223    void update();
224    void updateAndInformCPUInterfaces();
225
226  public:
227
228    Gicv3Distributor(Gicv3 * gic, uint32_t it_lines);
229
230    void deassertSPI(uint32_t int_id);
231    void init();
232    void initState();
233    uint64_t read(Addr addr, size_t size, bool is_secure_access);
234    void sendInt(uint32_t int_id);
235    void write(Addr addr, uint64_t data, size_t size,
236               bool is_secure_access);
237};
238
239#endif //__DEV_ARM_GICV3_DISTRIBUTOR_H__
240