gic_v3_distributor.hh revision 13756
12SN/A/* 21762SN/A * Copyright (c) 2018 Metempsy Technology Consulting 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Jairo Balart 292665Ssaidi@eecs.umich.edu */ 302SN/A 312SN/A#ifndef __DEV_ARM_GICV3_DISTRIBUTOR_H__ 322090SN/A#define __DEV_ARM_GICV3_DISTRIBUTOR_H__ 332090SN/A 342SN/A#include "base/addr_range.hh" 352502SN/A#include "dev/arm/gic_v3.hh" 362090SN/A#include "sim/serialize.hh" 372147SN/A 382166SN/Aclass Gicv3Distributor : public Serializable 392147SN/A{ 402167SN/A private: 412167SN/A 422167SN/A friend class Gicv3Redistributor; 432147SN/A friend class Gicv3CPUInterface; 442090SN/A 452222SN/A protected: 462090SN/A 472201SN/A Gicv3 * gic; 482201SN/A const uint32_t itLines; 492201SN/A 502112SN/A enum { 512174SN/A // Control Register 522198SN/A GICD_CTLR = 0x0000, 532174SN/A // Interrupt Controller Type Register 542175SN/A GICD_TYPER = 0x0004, 552222SN/A // Implementer Identification Register 562SN/A GICD_IIDR = 0x0008, 572SN/A // Error Reporting Status Register 582203SN/A GICD_STATUSR = 0x0010, 592166SN/A // Peripheral ID0 Register 602166SN/A GICD_PIDR0 = 0xffe0, 612203SN/A // Peripheral ID1 Register 622166SN/A GICD_PIDR1 = 0xffe4, 632222SN/A // Peripheral ID2 Register 642166SN/A GICD_PIDR2 = 0xffe8, 652203SN/A // Peripheral ID3 Register 662166SN/A GICD_PIDR3 = 0xffec, 672222SN/A // Peripheral ID4 Register 682203SN/A GICD_PIDR4 = 0xffd0, 692166SN/A // Peripheral ID5 Register 702166SN/A GICD_PIDR5 = 0xffd4, 712203SN/A // Peripheral ID6 Register 722166SN/A GICD_PIDR6 = 0xffd8, 732166SN/A // Peripheral ID7 Register 742203SN/A GICD_PIDR7 = 0xffdc, 752166SN/A }; 762222SN/A 772166SN/A // Interrupt Group Registers 782203SN/A static const AddrRange GICD_IGROUPR; 792166SN/A // Interrupt Set-Enable Registers 802222SN/A static const AddrRange GICD_ISENABLER; 812203SN/A // Interrupt Clear-Enable Registers 822166SN/A static const AddrRange GICD_ICENABLER; 832166SN/A // Interrupt Set-Pending Registers 842166SN/A static const AddrRange GICD_ISPENDR; 852166SN/A // Interrupt Clear-Pending Registers 862203SN/A static const AddrRange GICD_ICPENDR; 872166SN/A // Interrupt Set-Active Registers 882166SN/A static const AddrRange GICD_ISACTIVER; 892166SN/A // Interrupt Clear-Active Registers 902166SN/A static const AddrRange GICD_ICACTIVER; 912203SN/A // Interrupt Priority Registers 922166SN/A static const AddrRange GICD_IPRIORITYR; 932166SN/A // Interrupt Processor Targets Registers 942147SN/A static const AddrRange GICD_ITARGETSR; // GICv2 legacy 952090SN/A // Interrupt Configuration Registers 962147SN/A static const AddrRange GICD_ICFGR; 972147SN/A // Interrupt Group Modifier Registers 982147SN/A static const AddrRange GICD_IGRPMODR; 992222SN/A // Non-secure Access Control Registers 1002112SN/A static const AddrRange GICD_NSACR; 1012147SN/A // SGI Clear-Pending Registers 1022147SN/A static const AddrRange GICD_CPENDSGIR; // GICv2 legacy 1032222SN/A // SGI Set-Pending Registers 1042147SN/A static const AddrRange GICD_SPENDSGIR; // GICv2 legacy 1052090SN/A // Interrupt Routing Registers 1062147SN/A static const AddrRange GICD_IROUTER; 1072090SN/A 1082201SN/A BitUnion64(IROUTER) 1092201SN/A Bitfield<63, 40> res0_1; 1102147SN/A Bitfield<39, 32> Aff3; 1112147SN/A Bitfield<31> IRM; 1122147SN/A Bitfield<30, 24> res0_2; 1132222SN/A Bitfield<23, 16> Aff2; 1142112SN/A Bitfield<15, 8> Aff1; 1152147SN/A Bitfield<7, 0> Aff0; 1162147SN/A EndBitUnion(IROUTER) 1172222SN/A 1182203SN/A static const uint32_t GICD_CTLR_ENABLEGRP0 = 1 << 0; 1192201SN/A static const uint32_t GICD_CTLR_ENABLEGRP1 = 1 << 0; 1202203SN/A static const uint32_t GICD_CTLR_ENABLEGRP1NS = 1 << 1; 1212147SN/A static const uint32_t GICD_CTLR_ENABLEGRP1A = 1 << 1; 1222090SN/A static const uint32_t GICD_CTLR_ENABLEGRP1S = 1 << 2; 1232147SN/A static const uint32_t GICD_CTLR_DS = 1 << 6; 1242090SN/A 1252201SN/A bool ARE; 1262201SN/A bool DS; 1272147SN/A bool EnableGrp1S; 1282147SN/A bool EnableGrp1NS; 1292147SN/A bool EnableGrp0; 1302222SN/A std::vector <uint8_t> irqGroup; 1312112SN/A std::vector <bool> irqEnabled; 1322147SN/A std::vector <bool> irqPending; 1332147SN/A std::vector <bool> irqActive; 1342222SN/A std::vector <uint8_t> irqPriority; 1352147SN/A std::vector <Gicv3::IntTriggerType> irqConfig; 1362090SN/A std::vector <uint8_t> irqGrpmod; 1372502SN/A std::vector <uint8_t> irqNsacr; 1382502SN/A std::vector <IROUTER> irqAffinityRouting; 1392502SN/A 1402502SN/A public: 1412502SN/A 1422502SN/A static const uint32_t ADDR_RANGE_SIZE = 0x10000; 1432502SN/A 1442502SN/A protected: 1452502SN/A 1462502SN/A void activateIRQ(uint32_t int_id); 1472502SN/A void deactivateIRQ(uint32_t int_id); 1482502SN/A void fullUpdate(); 1492502SN/A Gicv3::GroupId getIntGroup(int int_id) const; 1502502SN/A 1512502SN/A inline bool 1522502SN/A groupEnabled(Gicv3::GroupId group) const 1532502SN/A { 1542502SN/A if (DS == 0) { 1552502SN/A switch (group) { 1562502SN/A case Gicv3::G0S: 1572502SN/A return EnableGrp0; 1582090SN/A 1592147SN/A case Gicv3::G1S: 1602147SN/A return EnableGrp1S; 1612147SN/A 1622222SN/A case Gicv3::G1NS: 1632112SN/A return EnableGrp1NS; 1642502SN/A 1652502SN/A default: 1662502SN/A panic("Gicv3Distributor::groupEnabled(): " 1672502SN/A "invalid group!\n"); 1682502SN/A } 1692147SN/A } else { 1702147SN/A switch (group) { 1712222SN/A case Gicv3::G0S: 1722147SN/A return EnableGrp0; 1732090SN/A 1742502SN/A case Gicv3::G1S: 1752090SN/A case Gicv3::G1NS: 1762147SN/A return EnableGrp1NS; 1772147SN/A 1782147SN/A default: 1792222SN/A panic("Gicv3Distributor::groupEnabled(): " 1802112SN/A "invalid group!\n"); 1812502SN/A } 1822502SN/A } 1832502SN/A } 1842502SN/A 1852502SN/A Gicv3::IntStatus intStatus(uint32_t int_id) const; 1862147SN/A 1872147SN/A inline bool isNotSPI(uint8_t int_id) const 1882222SN/A { 1892147SN/A if (int_id < (Gicv3::SGI_MAX + Gicv3::PPI_MAX) || int_id >= itLines) { 1902090SN/A return true; 1912502SN/A } else { 1922090SN/A return false; 1932147SN/A } 1942147SN/A } 1952147SN/A 1962222SN/A inline bool nsAccessToSecInt(uint8_t int_id, bool is_secure_access) const 1972112SN/A { 1982502SN/A return !DS && !is_secure_access && getIntGroup(int_id) != Gicv3::G1NS; 1992502SN/A } 2002502SN/A 2012502SN/A void reset(); 2022502SN/A void serialize(CheckpointOut & cp) const override; 2032147SN/A void unserialize(CheckpointIn & cp) override; 2042147SN/A void update(); 2052222SN/A void updateAndInformCPUInterfaces(); 2062147SN/A 2072090SN/A public: 2082502SN/A 2092090SN/A Gicv3Distributor(Gicv3 * gic, uint32_t it_lines); 2102147SN/A 2112147SN/A void deassertSPI(uint32_t int_id); 2122147SN/A void init(); 2132222SN/A void initState(); 2142112SN/A uint64_t read(Addr addr, size_t size, bool is_secure_access); 2152502SN/A void sendInt(uint32_t int_id); 2162502SN/A void write(Addr addr, uint64_t data, size_t size, 2172502SN/A bool is_secure_access); 2182502SN/A}; 2192502SN/A 2202147SN/A#endif //__DEV_ARM_GICV3_DISTRIBUTOR_H__ 2212147SN/A