gic_v3_cpu_interface.hh revision 14243:6116e1413f80
1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2018 Metempsy Technology Consulting
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Jairo Balart
41 */
42
43#ifndef __DEV_ARM_GICV3_CPU_INTERFACE_H__
44#define __DEV_ARM_GICV3_CPU_INTERFACE_H__
45
46#include "arch/arm/isa_device.hh"
47#include "dev/arm/gic_v3.hh"
48
49class Gicv3Distributor;
50class Gicv3Redistributor;
51
52class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
53{
54  private:
55
56    friend class Gicv3Distributor;
57    friend class Gicv3Redistributor;
58
59  protected:
60
61    Gicv3 * gic;
62    Gicv3Redistributor * redistributor;
63    Gicv3Distributor * distributor;
64    uint32_t cpuId;
65
66    ArmInterruptPin *maintenanceInterrupt;
67
68    BitUnion64(ICC_CTLR_EL1)
69        Bitfield<63, 20> res0_3;
70        Bitfield<19>     ExtRange;
71        Bitfield<18>     RSS;
72        Bitfield<17, 16> res0_2;
73        Bitfield<15>     A3V;
74        Bitfield<14>     SEIS;
75        Bitfield<13, 11> IDbits;
76        Bitfield<10, 8>  PRIbits;
77        Bitfield<7>      res0_1;
78        Bitfield<6>      PMHE;
79        Bitfield<5, 2>   res0_0;
80        Bitfield<1>      EOImode;
81        Bitfield<0>      CBPR;
82    EndBitUnion(ICC_CTLR_EL1)
83
84    BitUnion64(ICC_CTLR_EL3)
85        Bitfield<63, 20> res0_2;
86        Bitfield<19>     ExtRange;
87        Bitfield<18>     RSS;
88        Bitfield<17>     nDS;
89        Bitfield<16>     res0_1;
90        Bitfield<15>     A3V;
91        Bitfield<14>     SEIS;
92        Bitfield<13, 11> IDbits;
93        Bitfield<10, 8>  PRIbits;
94        Bitfield<7>      res0_0;
95        Bitfield<6>      PMHE;
96        Bitfield<5>      RM;
97        Bitfield<4>      EOImode_EL1NS;
98        Bitfield<3>      EOImode_EL1S;
99        Bitfield<2>      EOImode_EL3;
100        Bitfield<1>      CBPR_EL1NS;
101        Bitfield<0>      CBPR_EL1S;
102    EndBitUnion(ICC_CTLR_EL3)
103
104    BitUnion64(ICC_IGRPEN0_EL1)
105        Bitfield<63, 1> res0;
106        Bitfield<0>     Enable;
107    EndBitUnion(ICC_IGRPEN0_EL1)
108
109    BitUnion64(ICC_IGRPEN1_EL1)
110        Bitfield<63, 1> res0;
111        Bitfield<0>     Enable;
112    EndBitUnion(ICC_IGRPEN1_EL1)
113
114    BitUnion64(ICC_IGRPEN1_EL3)
115        Bitfield<63, 2> res0;
116        Bitfield<1>     EnableGrp1S;
117        Bitfield<0>     EnableGrp1NS;
118    EndBitUnion(ICC_IGRPEN1_EL3)
119
120    BitUnion64(ICC_SRE_EL1)
121        Bitfield<63, 3> res0;
122        Bitfield<2>     DIB;
123        Bitfield<1>     DFB;
124        Bitfield<0>     SRE;
125    EndBitUnion(ICC_SRE_EL1)
126
127    BitUnion64(ICC_SRE_EL2)
128        Bitfield<63, 4> res0;
129        Bitfield<3>     Enable;
130        Bitfield<2>     DIB;
131        Bitfield<1>     DFB;
132        Bitfield<0>     SRE;
133    EndBitUnion(ICC_SRE_EL2)
134
135    BitUnion64(ICC_SRE_EL3)
136        Bitfield<63, 4> res0;
137        Bitfield<3>     Enable;
138        Bitfield<2>     DIB;
139        Bitfield<1>     DFB;
140        Bitfield<0>     SRE;
141    EndBitUnion(ICC_SRE_EL3)
142
143    static const uint8_t PRIORITY_BITS = 5;
144
145    // Minimum BPR for Secure, or when security not enabled
146    static const uint8_t GIC_MIN_BPR = 2;
147    //  Minimum BPR for Nonsecure when security is enabled
148    static const uint8_t GIC_MIN_BPR_NS = GIC_MIN_BPR + 1;
149
150    static const uint8_t VIRTUAL_PRIORITY_BITS   = 5;
151    static const uint8_t VIRTUAL_PREEMPTION_BITS = 5;
152    static const uint8_t VIRTUAL_NUM_LIST_REGS   = 16;
153
154    static const uint8_t GIC_MIN_VBPR = 7 - VIRTUAL_PREEMPTION_BITS;
155
156    typedef struct {
157        uint32_t intid;
158        uint8_t prio;
159        Gicv3::GroupId group;
160    } hppi_t;
161
162    hppi_t hppi;
163
164    // GIC CPU interface memory mapped control registers (legacy)
165    enum {
166        GICC_CTLR    = 0x0000,
167        GICC_PMR     = 0x0004,
168        GICC_BPR     = 0x0008,
169        GICC_IAR     = 0x000C,
170        GICC_EOIR    = 0x0010,
171        GICC_RPR     = 0x0014,
172        GICC_HPPI    = 0x0018,
173        GICC_ABPR    = 0x001C,
174        GICC_AIAR    = 0x0020,
175        GICC_AEOIR   = 0x0024,
176        GICC_AHPPIR  = 0x0028,
177        GICC_STATUSR = 0x002C,
178        GICC_IIDR    = 0x00FC,
179    };
180
181    static const AddrRange GICC_APR;
182    static const AddrRange GICC_NSAPR;
183
184    // GIC CPU virtual interface memory mapped control registers (legacy)
185    enum {
186        GICH_HCR   = 0x0000,
187        GICH_VTR   = 0x0004,
188        GICH_VMCR  = 0x0008,
189        GICH_MISR  = 0x0010,
190        GICH_EISR  = 0x0020,
191        GICH_ELRSR = 0x0030,
192    };
193
194    static const AddrRange GICH_APR;
195    static const AddrRange GICH_LR;
196
197    BitUnion64(ICH_HCR_EL2)
198        Bitfield<63, 32> res0_2;
199        Bitfield<31, 27> EOIcount;
200        Bitfield<26, 15> res0_1;
201        Bitfield<14>     TDIR;
202        Bitfield<13>     TSEI;
203        Bitfield<12>     TALL1;
204        Bitfield<11>     TALL0;
205        Bitfield<10>     TC;
206        Bitfield<9, 8>   res0_0;
207        Bitfield<7>      VGrp1DIE;
208        Bitfield<6>      VGrp1EIE;
209        Bitfield<5>      VGrp0DIE;
210        Bitfield<4>      VGrp0EIE;
211        Bitfield<3>      NPIE;
212        Bitfield<2>      LRENPIE;
213        Bitfield<1>      UIE;
214        Bitfield<0>      En;
215    EndBitUnion(ICH_HCR_EL2)
216
217    BitUnion64(ICH_LR_EL2)
218        Bitfield<63, 62> State;
219        Bitfield<61>     HW;
220        Bitfield<60>     Group;
221        Bitfield<59, 56> res0_1;
222        Bitfield<55, 48> Priority;
223        Bitfield<47, 45> res0_0;
224        Bitfield<44, 32> pINTID;
225        Bitfield<41>     EOI;
226        Bitfield<31, 0>  vINTID;
227    EndBitUnion(ICH_LR_EL2)
228
229    static const uint64_t ICH_LR_EL2_STATE_INVALID        = 0;
230    static const uint64_t ICH_LR_EL2_STATE_PENDING        = 1;
231    static const uint64_t ICH_LR_EL2_STATE_ACTIVE         = 2;
232    static const uint64_t ICH_LR_EL2_STATE_ACTIVE_PENDING = 3;
233
234    BitUnion32(ICH_LRC)
235        Bitfield<31, 30> State;
236        Bitfield<29>     HW;
237        Bitfield<28>     Group;
238        Bitfield<27, 24> res0_1;
239        Bitfield<23, 16> Priority;
240        Bitfield<15, 13> res0_0;
241        Bitfield<12, 0>  pINTID;
242        Bitfield<9>      EOI;
243    EndBitUnion(ICH_LRC)
244
245    BitUnion64(ICH_MISR_EL2)
246        Bitfield<63, 8> res0;
247        Bitfield<7>     VGrp1D;
248        Bitfield<6>     VGrp1E;
249        Bitfield<5>     VGrp0D;
250        Bitfield<4>     VGrp0E;
251        Bitfield<3>     NP;
252        Bitfield<2>     LRENP;
253        Bitfield<1>     U;
254        Bitfield<0>     EOI;
255    EndBitUnion(ICH_MISR_EL2)
256
257    BitUnion64(ICH_VMCR_EL2)
258        Bitfield<63, 32> res0_2;
259        Bitfield<31, 24> VPMR;
260        Bitfield<23, 21> VBPR0;
261        Bitfield<20, 18> VBPR1;
262        Bitfield<17, 10> res0_1;
263        Bitfield<9>      VEOIM;
264        Bitfield<8, 5>   res0_0;
265        Bitfield<4>      VCBPR;
266        Bitfield<3>      VFIQEn;
267        Bitfield<2>      VAckCtl;
268        Bitfield<1>      VENG1;
269        Bitfield<0>      VENG0;
270    EndBitUnion(ICH_VMCR_EL2)
271
272    BitUnion64(ICH_VTR_EL2)
273        Bitfield<63, 32> res0_1;
274        Bitfield<31, 29> PRIbits;
275        Bitfield<28, 26> PREbits;
276        Bitfield<25, 23> IDbits;
277        Bitfield<22>     SEIS;
278        Bitfield<21>     A3V;
279        Bitfield<20>     res1;
280        Bitfield<19>     TDS;
281        Bitfield<18, 5>  res0_0;
282        Bitfield<4, 0>   ListRegs;
283    EndBitUnion(ICH_VTR_EL2)
284
285    BitUnion64(ICV_CTLR_EL1)
286        Bitfield<63, 19> res0_2;
287        Bitfield<18>     RSS;
288        Bitfield<17, 16> res0_1;
289        Bitfield<15>     A3V;
290        Bitfield<14>     SEIS;
291        Bitfield<13, 11> IDbits;
292        Bitfield<10, 8>  PRIbits;
293        Bitfield<7, 2>   res0_0;
294        Bitfield<1>      EOImode;
295        Bitfield<0>      CBPR;
296    EndBitUnion(ICV_CTLR_EL1)
297
298  protected:
299
300    void activateIRQ(uint32_t intid, Gicv3::GroupId group);
301    void generateSGI(RegVal val, Gicv3::GroupId group);
302    int currEL() const;
303    void deactivateIRQ(uint32_t intid, Gicv3::GroupId group);
304    void dropPriority(Gicv3::GroupId group);
305    uint64_t eoiMaintenanceInterruptStatus() const;
306    bool getHCREL2FMO() const;
307    bool getHCREL2IMO() const;
308    uint32_t getHPPIR0() const;
309    uint32_t getHPPIR1() const;
310    int getHPPVILR() const;
311    bool groupEnabled(Gicv3::GroupId group) const;
312    uint32_t groupPriorityMask(Gicv3::GroupId group);
313    bool haveEL(ArmISA::ExceptionLevel el) const;
314    int highestActiveGroup() const;
315    uint8_t highestActivePriority() const;
316    bool hppiCanPreempt();
317    bool hppviCanPreempt(int lrIdx) const;
318    bool inSecureState() const;
319    ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const;
320    bool isAA64() const;
321    bool isEL3OrMon() const;
322    bool isEOISplitMode() const;
323    bool isSecureBelowEL3() const;
324    ICH_MISR_EL2 maintenanceInterruptStatus() const;
325    void reset();
326    void serialize(CheckpointOut & cp) const override;
327    void unserialize(CheckpointIn & cp) override;
328    void update();
329    void updateDistributor();
330    void virtualActivateIRQ(uint32_t lrIdx);
331    void virtualDeactivateIRQ(int lrIdx);
332    uint8_t virtualDropPriority();
333    int virtualFindActive(uint32_t intid) const;
334    uint32_t virtualGroupPriorityMask(Gicv3::GroupId group) const;
335    uint8_t virtualHighestActivePriority() const;
336    void virtualIncrementEOICount();
337    bool virtualIsEOISplitMode() const;
338    void virtualUpdate();
339    RegVal bpr1(Gicv3::GroupId group);
340
341    RegVal readBankedMiscReg(MiscRegIndex misc_reg) const;
342    void setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const;
343  public:
344
345    Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
346
347    void init();
348    void initState();
349
350  public: // BaseISADevice
351    RegVal readMiscReg(int misc_reg) override;
352    void setMiscReg(int misc_reg, RegVal val) override;
353    void setThreadContext(ThreadContext *tc) override;
354};
355
356#endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__
357