gic_v3_cpu_interface.hh revision 13826:34a9929c35eb 
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Jairo Balart
29 */
30
31#ifndef __DEV_ARM_GICV3_CPU_INTERFACE_H__
32#define __DEV_ARM_GICV3_CPU_INTERFACE_H__
33
34#include "arch/arm/isa_device.hh"
35#include "dev/arm/gic_v3.hh"
36
37class Gicv3Distributor;
38class Gicv3Redistributor;
39
40class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
41{
42  private:
43
44    friend class Gicv3Distributor;
45    friend class Gicv3Redistributor;
46
47  protected:
48
49    Gicv3 * gic;
50    Gicv3Redistributor * redistributor;
51    Gicv3Distributor * distributor;
52    uint32_t cpuId;
53
54    ArmInterruptPin *maintenanceInterrupt;
55
56    BitUnion64(ICC_CTLR_EL1)
57        Bitfield<63, 20> res0_3;
58        Bitfield<19>     ExtRange;
59        Bitfield<18>     RSS;
60        Bitfield<17, 16> res0_2;
61        Bitfield<15>     A3V;
62        Bitfield<14>     SEIS;
63        Bitfield<13, 11> IDbits;
64        Bitfield<10, 8>  PRIbits;
65        Bitfield<7>      res0_1;
66        Bitfield<6>      PMHE;
67        Bitfield<5, 2>   res0_0;
68        Bitfield<1>      EOImode;
69        Bitfield<0>      CBPR;
70    EndBitUnion(ICC_CTLR_EL1)
71
72    BitUnion64(ICC_CTLR_EL3)
73        Bitfield<63, 20> res0_2;
74        Bitfield<19>     ExtRange;
75        Bitfield<18>     RSS;
76        Bitfield<17>     nDS;
77        Bitfield<16>     res0_1;
78        Bitfield<15>     A3V;
79        Bitfield<14>     SEIS;
80        Bitfield<13, 11> IDbits;
81        Bitfield<10, 8>  PRIbits;
82        Bitfield<7>      res0_0;
83        Bitfield<6>      PMHE;
84        Bitfield<5>      RM;
85        Bitfield<4>      EOImode_EL1NS;
86        Bitfield<3>      EOImode_EL1S;
87        Bitfield<2>      EOImode_EL3;
88        Bitfield<1>      CBPR_EL1NS;
89        Bitfield<0>      CBPR_EL1S;
90    EndBitUnion(ICC_CTLR_EL3)
91
92    BitUnion64(ICC_IGRPEN0_EL1)
93        Bitfield<63, 1> res0;
94        Bitfield<0>     Enable;
95    EndBitUnion(ICC_IGRPEN0_EL1)
96
97    BitUnion64(ICC_IGRPEN1_EL1)
98        Bitfield<63, 1> res0;
99        Bitfield<0>     Enable;
100    EndBitUnion(ICC_IGRPEN1_EL1)
101
102    BitUnion64(ICC_IGRPEN1_EL3)
103        Bitfield<63, 2> res0;
104        Bitfield<1>     EnableGrp1S;
105        Bitfield<0>     EnableGrp1NS;
106    EndBitUnion(ICC_IGRPEN1_EL3)
107
108    BitUnion64(ICC_SRE_EL1)
109        Bitfield<63, 3> res0;
110        Bitfield<2>     DIB;
111        Bitfield<1>     DFB;
112        Bitfield<0>     SRE;
113    EndBitUnion(ICC_SRE_EL1)
114
115    BitUnion64(ICC_SRE_EL2)
116        Bitfield<63, 4> res0;
117        Bitfield<3>     Enable;
118        Bitfield<2>     DIB;
119        Bitfield<1>     DFB;
120        Bitfield<0>     SRE;
121    EndBitUnion(ICC_SRE_EL2)
122
123    BitUnion64(ICC_SRE_EL3)
124        Bitfield<63, 4> res0;
125        Bitfield<3>     Enable;
126        Bitfield<2>     DIB;
127        Bitfield<1>     DFB;
128        Bitfield<0>     SRE;
129    EndBitUnion(ICC_SRE_EL3)
130
131    static const uint8_t PRIORITY_BITS = 5;
132
133    // Minimum BPR for Secure, or when security not enabled
134    static const uint8_t GIC_MIN_BPR = 2;
135    //  Minimum BPR for Nonsecure when security is enabled
136    static const uint8_t GIC_MIN_BPR_NS = GIC_MIN_BPR + 1;
137
138    static const uint8_t VIRTUAL_PRIORITY_BITS   = 5;
139    static const uint8_t VIRTUAL_PREEMPTION_BITS = 5;
140    static const uint8_t VIRTUAL_NUM_LIST_REGS   = 16;
141
142    static const uint8_t GIC_MIN_VBPR = 7 - VIRTUAL_PREEMPTION_BITS;
143
144    typedef struct {
145        uint32_t intid;
146        uint8_t prio;
147        Gicv3::GroupId group;
148    } hppi_t;
149
150    hppi_t hppi;
151
152    // GIC CPU interface memory mapped control registers (legacy)
153    enum {
154        GICC_CTLR    = 0x0000,
155        GICC_PMR     = 0x0004,
156        GICC_BPR     = 0x0008,
157        GICC_IAR     = 0x000C,
158        GICC_EOIR    = 0x0010,
159        GICC_RPR     = 0x0014,
160        GICC_HPPI    = 0x0018,
161        GICC_ABPR    = 0x001C,
162        GICC_AIAR    = 0x0020,
163        GICC_AEOIR   = 0x0024,
164        GICC_AHPPIR  = 0x0028,
165        GICC_STATUSR = 0x002C,
166        GICC_IIDR    = 0x00FC,
167    };
168
169    static const AddrRange GICC_APR;
170    static const AddrRange GICC_NSAPR;
171
172    // GIC CPU virtual interface memory mapped control registers (legacy)
173    enum {
174        GICH_HCR   = 0x0000,
175        GICH_VTR   = 0x0004,
176        GICH_VMCR  = 0x0008,
177        GICH_MISR  = 0x0010,
178        GICH_EISR  = 0x0020,
179        GICH_ELRSR = 0x0030,
180    };
181
182    static const AddrRange GICH_APR;
183    static const AddrRange GICH_LR;
184
185    BitUnion64(ICH_HCR_EL2)
186        Bitfield<63, 32> res0_2;
187        Bitfield<31, 27> EOIcount;
188        Bitfield<26, 15> res0_1;
189        Bitfield<14>     TDIR;
190        Bitfield<13>     TSEI;
191        Bitfield<12>     TALL1;
192        Bitfield<11>     TALL0;
193        Bitfield<10>     TC;
194        Bitfield<9, 8>   res0_0;
195        Bitfield<7>      VGrp1DIE;
196        Bitfield<6>      VGrp1EIE;
197        Bitfield<5>      VGrp0DIE;
198        Bitfield<4>      VGrp0EIE;
199        Bitfield<3>      NPIE;
200        Bitfield<2>      LRENPIE;
201        Bitfield<1>      UIE;
202        Bitfield<0>      En;
203    EndBitUnion(ICH_HCR_EL2)
204
205    BitUnion64(ICH_LR_EL2)
206        Bitfield<63, 62> State;
207        Bitfield<61>     HW;
208        Bitfield<60>     Group;
209        Bitfield<59, 56> res0_1;
210        Bitfield<55, 48> Priority;
211        Bitfield<47, 45> res0_0;
212        Bitfield<44, 32> pINTID;
213        Bitfield<41>     EOI;
214        Bitfield<31, 0>  vINTID;
215    EndBitUnion(ICH_LR_EL2)
216
217    static const uint64_t ICH_LR_EL2_STATE_INVALID        = 0;
218    static const uint64_t ICH_LR_EL2_STATE_PENDING        = 1;
219    static const uint64_t ICH_LR_EL2_STATE_ACTIVE         = 2;
220    static const uint64_t ICH_LR_EL2_STATE_ACTIVE_PENDING = 3;
221
222    BitUnion32(ICH_LRC)
223        Bitfield<31, 30> State;
224        Bitfield<29>     HW;
225        Bitfield<28>     Group;
226        Bitfield<27, 24> res0_1;
227        Bitfield<23, 16> Priority;
228        Bitfield<15, 13> res0_0;
229        Bitfield<12, 0>  pINTID;
230        Bitfield<9>      EOI;
231    EndBitUnion(ICH_LRC)
232
233    BitUnion64(ICH_MISR_EL2)
234        Bitfield<63, 8> res0;
235        Bitfield<7>     VGrp1D;
236        Bitfield<6>     VGrp1E;
237        Bitfield<5>     VGrp0D;
238        Bitfield<4>     VGrp0E;
239        Bitfield<3>     NP;
240        Bitfield<2>     LRENP;
241        Bitfield<1>     U;
242        Bitfield<0>     EOI;
243    EndBitUnion(ICH_MISR_EL2)
244
245    BitUnion64(ICH_VMCR_EL2)
246        Bitfield<63, 32> res0_2;
247        Bitfield<31, 24> VPMR;
248        Bitfield<23, 21> VBPR0;
249        Bitfield<20, 18> VBPR1;
250        Bitfield<17, 10> res0_1;
251        Bitfield<9>      VEOIM;
252        Bitfield<8, 5>   res0_0;
253        Bitfield<4>      VCBPR;
254        Bitfield<3>      VFIQEn;
255        Bitfield<2>      VAckCtl;
256        Bitfield<1>      VENG1;
257        Bitfield<0>      VENG0;
258    EndBitUnion(ICH_VMCR_EL2)
259
260    BitUnion64(ICH_VTR_EL2)
261        Bitfield<63, 32> res0_1;
262        Bitfield<31, 29> PRIbits;
263        Bitfield<28, 26> PREbits;
264        Bitfield<25, 23> IDbits;
265        Bitfield<22>     SEIS;
266        Bitfield<21>     A3V;
267        Bitfield<20>     res1;
268        Bitfield<19>     TDS;
269        Bitfield<18, 5>  res0_0;
270        Bitfield<4, 0>   ListRegs;
271    EndBitUnion(ICH_VTR_EL2)
272
273    BitUnion64(ICV_CTLR_EL1)
274        Bitfield<63, 19> res0_2;
275        Bitfield<18>     RSS;
276        Bitfield<17, 16> res0_1;
277        Bitfield<15>     A3V;
278        Bitfield<14>     SEIS;
279        Bitfield<13, 11> IDbits;
280        Bitfield<10, 8>  PRIbits;
281        Bitfield<7, 2>   res0_0;
282        Bitfield<1>      EOImode;
283        Bitfield<0>      CBPR;
284    EndBitUnion(ICV_CTLR_EL1)
285
286  protected:
287
288    void activateIRQ(uint32_t intid, Gicv3::GroupId group);
289    int currEL() const;
290    void deactivateIRQ(uint32_t intid, Gicv3::GroupId group);
291    void dropPriority(Gicv3::GroupId group);
292    uint64_t eoiMaintenanceInterruptStatus() const;
293    bool getHCREL2FMO() const;
294    bool getHCREL2IMO() const;
295    uint32_t getHPPIR0() const;
296    uint32_t getHPPIR1() const;
297    int getHPPVILR() const;
298    bool groupEnabled(Gicv3::GroupId group) const;
299    uint32_t groupPriorityMask(Gicv3::GroupId group) const;
300    bool haveEL(ArmISA::ExceptionLevel el) const;
301    int highestActiveGroup() const;
302    uint8_t highestActivePriority() const;
303    bool hppiCanPreempt() const;
304    bool hppviCanPreempt(int lrIdx) const;
305    bool inSecureState() const;
306    ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const;
307    bool isAA64() const;
308    bool isEL3OrMon() const;
309    bool isEOISplitMode() const;
310    bool isSecureBelowEL3() const;
311    ICH_MISR_EL2 maintenanceInterruptStatus() const;
312    void reset();
313    void serialize(CheckpointOut & cp) const override;
314    void unserialize(CheckpointIn & cp) override;
315    void update();
316    void virtualActivateIRQ(uint32_t lrIdx);
317    void virtualDeactivateIRQ(int lrIdx);
318    uint8_t virtualDropPriority();
319    int virtualFindActive(uint32_t intid) const;
320    uint32_t virtualGroupPriorityMask(Gicv3::GroupId group) const;
321    uint8_t virtualHighestActivePriority() const;
322    void virtualIncrementEOICount();
323    bool virtualIsEOISplitMode() const;
324    void virtualUpdate();
325
326  public:
327
328    Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
329
330    void init();
331    void initState();
332
333  public: // BaseISADevice
334    RegVal readMiscReg(int misc_reg) override;
335    void setMiscReg(int misc_reg, RegVal val) override;
336    void setThreadContext(ThreadContext *tc) override;
337};
338
339#endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__
340