gic_v3_cpu_interface.hh revision 13760:fcec3c5abbdf 
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Jairo Balart
29 */
30
31#ifndef __DEV_ARM_GICV3_CPU_INTERFACE_H__
32#define __DEV_ARM_GICV3_CPU_INTERFACE_H__
33
34#include "arch/arm/isa_device.hh"
35#include "dev/arm/gic_v3.hh"
36
37class Gicv3Distributor;
38class Gicv3Redistributor;
39
40class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
41{
42  private:
43
44    friend class Gicv3Distributor;
45    friend class Gicv3Redistributor;
46
47  protected:
48
49    Gicv3 * gic;
50    Gicv3Redistributor * redistributor;
51    Gicv3Distributor * distributor;
52    uint32_t cpuId;
53
54    BitUnion64(ICC_CTLR_EL1)
55        Bitfield<63, 20> res0_3;
56        Bitfield<19>     ExtRange;
57        Bitfield<18>     RSS;
58        Bitfield<17, 16> res0_2;
59        Bitfield<15>     A3V;
60        Bitfield<14>     SEIS;
61        Bitfield<13, 11> IDbits;
62        Bitfield<10, 8>  PRIbits;
63        Bitfield<7>      res0_1;
64        Bitfield<6>      PMHE;
65        Bitfield<5, 2>   res0_0;
66        Bitfield<1>      EOImode;
67        Bitfield<0>      CBPR;
68    EndBitUnion(ICC_CTLR_EL1)
69
70    BitUnion64(ICC_CTLR_EL3)
71        Bitfield<63, 20> res0_2;
72        Bitfield<19>     ExtRange;
73        Bitfield<18>     RSS;
74        Bitfield<17>     nDS;
75        Bitfield<16>     res0_1;
76        Bitfield<15>     A3V;
77        Bitfield<14>     SEIS;
78        Bitfield<13, 11> IDbits;
79        Bitfield<10, 8>  PRIbits;
80        Bitfield<7>      res0_0;
81        Bitfield<6>      PMHE;
82        Bitfield<5>      RM;
83        Bitfield<4>      EOImode_EL1NS;
84        Bitfield<3>      EOImode_EL1S;
85        Bitfield<2>      EOImode_EL3;
86        Bitfield<1>      CBPR_EL1NS;
87        Bitfield<0>      CBPR_EL1S;
88    EndBitUnion(ICC_CTLR_EL3)
89
90    BitUnion64(ICC_IGRPEN0_EL1)
91        Bitfield<63, 1> res0;
92        Bitfield<0>     Enable;
93    EndBitUnion(ICC_IGRPEN0_EL1)
94
95    BitUnion64(ICC_IGRPEN1_EL1)
96        Bitfield<63, 1> res0;
97        Bitfield<0>     Enable;
98    EndBitUnion(ICC_IGRPEN1_EL1)
99
100    BitUnion64(ICC_IGRPEN1_EL3)
101        Bitfield<63, 2> res0;
102        Bitfield<1>     EnableGrp1S;
103        Bitfield<0>     EnableGrp1NS;
104    EndBitUnion(ICC_IGRPEN1_EL3)
105
106    BitUnion64(ICC_SRE_EL1)
107        Bitfield<63, 3> res0;
108        Bitfield<2>     DIB;
109        Bitfield<1>     DFB;
110        Bitfield<0>     SRE;
111    EndBitUnion(ICC_SRE_EL1)
112
113    BitUnion64(ICC_SRE_EL2)
114        Bitfield<63, 4> res0;
115        Bitfield<3>     Enable;
116        Bitfield<2>     DIB;
117        Bitfield<1>     DFB;
118        Bitfield<0>     SRE;
119    EndBitUnion(ICC_SRE_EL2)
120
121    BitUnion64(ICC_SRE_EL3)
122        Bitfield<63, 4> res0;
123        Bitfield<3>     Enable;
124        Bitfield<2>     DIB;
125        Bitfield<1>     DFB;
126        Bitfield<0>     SRE;
127    EndBitUnion(ICC_SRE_EL3)
128
129    static const uint8_t PRIORITY_BITS = 5;
130
131    // Minimum BPR for Secure, or when security not enabled
132    static const uint8_t GIC_MIN_BPR = 2;
133    //  Minimum BPR for Nonsecure when security is enabled
134    static const uint8_t GIC_MIN_BPR_NS = GIC_MIN_BPR + 1;
135
136    static const uint8_t VIRTUAL_PRIORITY_BITS   = 5;
137    static const uint8_t VIRTUAL_PREEMPTION_BITS = 5;
138    static const uint8_t VIRTUAL_NUM_LIST_REGS   = 16;
139
140    static const uint8_t GIC_MIN_VBPR = 7 - VIRTUAL_PREEMPTION_BITS;
141
142    typedef struct {
143        uint32_t intid;
144        uint8_t prio;
145        Gicv3::GroupId group;
146    } hppi_t;
147
148    hppi_t hppi;
149
150    // GIC CPU interface memory mapped control registers (legacy)
151    enum {
152        GICC_CTLR    = 0x0000,
153        GICC_PMR     = 0x0004,
154        GICC_BPR     = 0x0008,
155        GICC_IAR     = 0x000C,
156        GICC_EOIR    = 0x0010,
157        GICC_RPR     = 0x0014,
158        GICC_HPPI    = 0x0018,
159        GICC_ABPR    = 0x001C,
160        GICC_AIAR    = 0x0020,
161        GICC_AEOIR   = 0x0024,
162        GICC_AHPPIR  = 0x0028,
163        GICC_STATUSR = 0x002C,
164        GICC_IIDR    = 0x00FC,
165    };
166
167    static const AddrRange GICC_APR;
168    static const AddrRange GICC_NSAPR;
169
170    // GIC CPU virtual interface memory mapped control registers (legacy)
171    enum {
172        GICH_HCR   = 0x0000,
173        GICH_VTR   = 0x0004,
174        GICH_VMCR  = 0x0008,
175        GICH_MISR  = 0x0010,
176        GICH_EISR  = 0x0020,
177        GICH_ELRSR = 0x0030,
178    };
179
180    static const AddrRange GICH_APR;
181    static const AddrRange GICH_LR;
182
183    BitUnion64(ICH_HCR_EL2)
184        Bitfield<63, 32> res0_2;
185        Bitfield<31, 27> EOIcount;
186        Bitfield<26, 15> res0_1;
187        Bitfield<14>     TDIR;
188        Bitfield<13>     TSEI;
189        Bitfield<12>     TALL1;
190        Bitfield<11>     TALL0;
191        Bitfield<10>     TC;
192        Bitfield<9, 8>   res0_0;
193        Bitfield<7>      VGrp1DIE;
194        Bitfield<6>      VGrp1EIE;
195        Bitfield<5>      VGrp0DIE;
196        Bitfield<4>      VGrp0EIE;
197        Bitfield<3>      NPIE;
198        Bitfield<2>      LRENPIE;
199        Bitfield<1>      UIE;
200        Bitfield<0>      En;
201    EndBitUnion(ICH_HCR_EL2)
202
203    BitUnion64(ICH_LR_EL2)
204        Bitfield<63, 62> State;
205        Bitfield<61>     HW;
206        Bitfield<60>     Group;
207        Bitfield<59, 56> res0_1;
208        Bitfield<55, 48> Priority;
209        Bitfield<47, 45> res0_0;
210        Bitfield<44, 32> pINTID;
211        Bitfield<41>     EOI;
212        Bitfield<31, 0>  vINTID;
213    EndBitUnion(ICH_LR_EL2)
214
215    static const uint64_t ICH_LR_EL2_STATE_INVALID        = 0;
216    static const uint64_t ICH_LR_EL2_STATE_PENDING        = 1;
217    static const uint64_t ICH_LR_EL2_STATE_ACTIVE         = 2;
218    static const uint64_t ICH_LR_EL2_STATE_ACTIVE_PENDING = 3;
219
220    BitUnion32(ICH_LRC)
221        Bitfield<31, 30> State;
222        Bitfield<29>     HW;
223        Bitfield<28>     Group;
224        Bitfield<27, 24> res0_1;
225        Bitfield<23, 16> Priority;
226        Bitfield<15, 13> res0_0;
227        Bitfield<12, 0>  pINTID;
228        Bitfield<9>      EOI;
229    EndBitUnion(ICH_LRC)
230
231    BitUnion64(ICH_MISR_EL2)
232        Bitfield<63, 8> res0;
233        Bitfield<7>     VGrp1D;
234        Bitfield<6>     VGrp1E;
235        Bitfield<5>     VGrp0D;
236        Bitfield<4>     VGrp0E;
237        Bitfield<3>     NP;
238        Bitfield<2>     LRENP;
239        Bitfield<1>     U;
240        Bitfield<0>     EOI;
241    EndBitUnion(ICH_MISR_EL2)
242
243    BitUnion64(ICH_VMCR_EL2)
244        Bitfield<63, 32> res0_2;
245        Bitfield<31, 24> VPMR;
246        Bitfield<23, 21> VBPR0;
247        Bitfield<20, 18> VBPR1;
248        Bitfield<17, 10> res0_1;
249        Bitfield<9>      VEOIM;
250        Bitfield<8, 5>   res0_0;
251        Bitfield<4>      VCBPR;
252        Bitfield<3>      VFIQEn;
253        Bitfield<2>      VAckCtl;
254        Bitfield<1>      VENG1;
255        Bitfield<0>      VENG0;
256    EndBitUnion(ICH_VMCR_EL2)
257
258    BitUnion64(ICH_VTR_EL2)
259        Bitfield<63, 32> res0_1;
260        Bitfield<31, 29> PRIbits;
261        Bitfield<28, 26> PREbits;
262        Bitfield<25, 23> IDbits;
263        Bitfield<22>     SEIS;
264        Bitfield<21>     A3V;
265        Bitfield<20>     res1;
266        Bitfield<19>     TDS;
267        Bitfield<18, 5>  res0_0;
268        Bitfield<4, 0>   ListRegs;
269    EndBitUnion(ICH_VTR_EL2)
270
271    BitUnion64(ICV_CTLR_EL1)
272        Bitfield<63, 19> res0_2;
273        Bitfield<18>     RSS;
274        Bitfield<17, 16> res0_1;
275        Bitfield<15>     A3V;
276        Bitfield<14>     SEIS;
277        Bitfield<13, 11> IDbits;
278        Bitfield<10, 8>  PRIbits;
279        Bitfield<7, 2>   res0_0;
280        Bitfield<1>      EOImode;
281        Bitfield<0>      CBPR;
282    EndBitUnion(ICV_CTLR_EL1)
283
284  protected:
285
286    void activateIRQ(uint32_t intid, Gicv3::GroupId group);
287    int currEL() const;
288    void deactivateIRQ(uint32_t intid, Gicv3::GroupId group);
289    void dropPriority(Gicv3::GroupId group);
290    uint64_t eoiMaintenanceInterruptStatus() const;
291    bool getHCREL2FMO() const;
292    bool getHCREL2IMO() const;
293    uint32_t getHPPIR0() const;
294    uint32_t getHPPIR1() const;
295    int getHPPVILR() const;
296    bool groupEnabled(Gicv3::GroupId group) const;
297    uint32_t groupPriorityMask(Gicv3::GroupId group) const;
298    bool haveEL(ArmISA::ExceptionLevel el) const;
299    int highestActiveGroup() const;
300    uint8_t highestActivePriority() const;
301    bool hppiCanPreempt() const;
302    bool hppviCanPreempt(int lrIdx) const;
303    bool inSecureState() const;
304    ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const;
305    bool isAA64() const;
306    bool isEL3OrMon() const;
307    bool isEOISplitMode() const;
308    bool isSecureBelowEL3() const;
309    ICH_MISR_EL2 maintenanceInterruptStatus() const;
310    RegVal readMiscReg(int misc_reg) override;
311    void reset();
312    void serialize(CheckpointOut & cp) const override;
313    void setMiscReg(int misc_reg, RegVal val) override;
314    void unserialize(CheckpointIn & cp) override;
315    void update();
316    void virtualActivateIRQ(uint32_t lrIdx);
317    void virtualDeactivateIRQ(int lrIdx);
318    uint8_t virtualDropPriority();
319    int virtualFindActive(uint32_t intid) const;
320    uint32_t virtualGroupPriorityMask(Gicv3::GroupId group) const;
321    uint8_t virtualHighestActivePriority() const;
322    void virtualIncrementEOICount();
323    bool virtualIsEOISplitMode() const;
324    void virtualUpdate();
325
326  public:
327
328    Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
329
330    void init();
331    void initState();
332};
333
334#endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__
335