generic_timer.hh revision 12101:f3e183c78529 
1/*
2 * Copyright (c) 2013, 2015, 2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Giacomo Gabrielli
38 *          Andreas Sandberg
39 */
40
41#ifndef __DEV_ARM_GENERIC_TIMER_HH__
42#define __DEV_ARM_GENERIC_TIMER_HH__
43
44#include "arch/arm/isa_device.hh"
45#include "base/bitunion.hh"
46#include "dev/arm/base_gic.hh"
47#include "sim/core.hh"
48#include "sim/sim_object.hh"
49
50/// @file
51/// This module implements the global system counter and the local per-CPU
52/// architected timers as specified by the ARM Generic Timer extension (ARM
53/// ARM, Issue C, Chapter 17).
54
55class Checkpoint;
56class GenericTimerParams;
57class GenericTimerMemParams;
58
59/// Global system counter.  It is shared by the architected timers.
60/// @todo: implement memory-mapped controls
61class SystemCounter : public Serializable
62{
63  protected:
64    /// Counter frequency (as specified by CNTFRQ).
65    uint64_t _freq;
66    /// Cached copy of the counter period (inverse of the frequency).
67    Tick _period;
68    /// Tick when the counter was reset.
69    Tick _resetTick;
70
71    uint32_t _regCntkctl;
72
73  public:
74    SystemCounter();
75
76    /// Returns the current value of the physical counter.
77    uint64_t value() const
78    {
79        if (_freq == 0)
80            return 0;  // Counter is still off.
81        return (curTick() - _resetTick) / _period;
82    }
83
84    /// Returns the counter frequency.
85    uint64_t freq() const { return _freq; }
86    /// Sets the counter frequency.
87    /// @param freq frequency in Hz.
88    void setFreq(uint32_t freq);
89
90    /// Returns the counter period.
91    Tick period() const { return _period; }
92
93    void setKernelControl(uint32_t val) { _regCntkctl = val; }
94    uint32_t getKernelControl() { return _regCntkctl; }
95
96    void serialize(CheckpointOut &cp) const override;
97    void unserialize(CheckpointIn &cp) override;
98
99  private:
100    // Disable copying
101    SystemCounter(const SystemCounter &c);
102};
103
104/// Per-CPU architected timer.
105class ArchTimer : public Serializable, public Drainable
106{
107  public:
108    class Interrupt
109    {
110      public:
111        Interrupt(BaseGic &gic, unsigned irq)
112            : _gic(gic), _ppi(false), _irq(irq), _cpu(0) {}
113
114        Interrupt(BaseGic &gic, unsigned irq, unsigned cpu)
115            : _gic(gic), _ppi(true), _irq(irq), _cpu(cpu) {}
116
117        void send();
118        void clear();
119
120      private:
121        BaseGic &_gic;
122        const bool _ppi;
123        const unsigned _irq;
124        const unsigned _cpu;
125    };
126
127  protected:
128    /// Control register.
129    BitUnion32(ArchTimerCtrl)
130    Bitfield<0> enable;
131    Bitfield<1> imask;
132    Bitfield<2> istatus;
133    EndBitUnion(ArchTimerCtrl)
134
135    /// Name of this timer.
136    const std::string _name;
137
138    /// Pointer to parent class.
139    SimObject &_parent;
140
141    SystemCounter &_systemCounter;
142
143    Interrupt _interrupt;
144
145    /// Value of the control register ({CNTP/CNTHP/CNTV}_CTL).
146    ArchTimerCtrl _control;
147    /// Programmed limit value for the upcounter ({CNTP/CNTHP/CNTV}_CVAL).
148    uint64_t _counterLimit;
149    /// Offset relative to the physical timer (CNTVOFF)
150    uint64_t _offset;
151
152    /**
153     * Timer settings or the offset has changed, re-evaluate
154     * trigger condition and raise interrupt if necessary.
155     */
156    void updateCounter();
157
158    /// Called when the upcounter reaches the programmed value.
159    void counterLimitReached();
160    EventFunctionWrapper _counterLimitReachedEvent;
161
162  public:
163    ArchTimer(const std::string &name,
164              SimObject &parent,
165              SystemCounter &sysctr,
166              const Interrupt &interrupt);
167
168    /// Returns the timer name.
169    std::string name() const { return _name; }
170
171    /// Returns the CompareValue view of the timer.
172    uint64_t compareValue() const { return _counterLimit; }
173    /// Sets the CompareValue view of the timer.
174    void setCompareValue(uint64_t val);
175
176    /// Returns the TimerValue view of the timer.
177    uint32_t timerValue() const { return _counterLimit - value(); }
178    /// Sets the TimerValue view of the timer.
179    void setTimerValue(uint32_t val);
180
181    /// Sets the control register.
182    uint32_t control() const { return _control; }
183    void setControl(uint32_t val);
184
185    uint64_t offset() const { return _offset; }
186    void setOffset(uint64_t val);
187
188    /// Returns the value of the counter which this timer relies on.
189    uint64_t value() const;
190
191    // Serializable
192    void serialize(CheckpointOut &cp) const override;
193    void unserialize(CheckpointIn &cp) override;
194
195    // Drainable
196    DrainState drain() override;
197    void drainResume() override;
198
199  private:
200    // Disable copying
201    ArchTimer(const ArchTimer &t);
202};
203
204class GenericTimer : public SimObject
205{
206  public:
207    GenericTimer(GenericTimerParams *p);
208
209    void serialize(CheckpointOut &cp) const override;
210    void unserialize(CheckpointIn &cp) override;
211
212  public:
213    void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val);
214    ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu);
215
216  protected:
217    struct CoreTimers {
218        CoreTimers(GenericTimer &parent, unsigned cpu,
219                   unsigned _irqPhys, unsigned _irqVirt)
220            : irqPhys(*parent.gic, _irqPhys, cpu),
221              irqVirt(*parent.gic, _irqVirt, cpu),
222              // This should really be phys_timerN, but we are stuck with
223              // arch_timer for backwards compatibility.
224              phys(csprintf("%s.arch_timer%d", parent.name(), cpu),
225                   parent, parent.systemCounter,
226                   irqPhys),
227              virt(csprintf("%s.virt_timer%d", parent.name(), cpu),
228                   parent, parent.systemCounter,
229                   irqVirt)
230        {}
231
232        ArchTimer::Interrupt irqPhys;
233        ArchTimer::Interrupt irqVirt;
234
235        ArchTimer phys;
236        ArchTimer virt;
237
238      private:
239        // Disable copying
240        CoreTimers(const CoreTimers &c);
241    };
242
243    CoreTimers &getTimers(int cpu_id);
244    void createTimers(unsigned cpus);
245
246    /// System counter.
247    SystemCounter systemCounter;
248
249    /// Per-CPU physical architected timers.
250    std::vector<std::unique_ptr<CoreTimers>> timers;
251
252  protected: // Configuration
253    /// Pointer to the GIC, needed to trigger timer interrupts.
254    BaseGic *const gic;
255
256    /// Physical timer interrupt
257    const unsigned irqPhys;
258
259    /// Virtual timer interrupt
260    const unsigned irqVirt;
261};
262
263class GenericTimerISA : public ArmISA::BaseISADevice
264{
265  public:
266    GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
267        : parent(_parent), cpu(_cpu) {}
268
269    void setMiscReg(int misc_reg, ArmISA::MiscReg val) override {
270        parent.setMiscReg(misc_reg, cpu, val);
271    }
272    ArmISA::MiscReg readMiscReg(int misc_reg) override {
273        return parent.readMiscReg(misc_reg, cpu);
274    }
275
276  protected:
277    GenericTimer &parent;
278    unsigned cpu;
279};
280
281class GenericTimerMem : public PioDevice
282{
283  public:
284    GenericTimerMem(GenericTimerMemParams *p);
285
286    void serialize(CheckpointOut &cp) const override;
287    void unserialize(CheckpointIn &cp) override;
288
289  public: // PioDevice
290    AddrRangeList getAddrRanges() const override { return addrRanges; }
291    Tick read(PacketPtr pkt) override;
292    Tick write(PacketPtr pkt) override;
293
294  protected:
295    uint64_t ctrlRead(Addr addr, size_t size) const;
296    void ctrlWrite(Addr addr, size_t size, uint64_t value);
297
298    uint64_t timerRead(Addr addr, size_t size) const;
299    void timerWrite(Addr addr, size_t size, uint64_t value);
300
301  protected: // Registers
302    static const Addr CTRL_CNTFRQ          = 0x000;
303    static const Addr CTRL_CNTNSAR         = 0x004;
304    static const Addr CTRL_CNTTIDR         = 0x008;
305    static const Addr CTRL_CNTACR_BASE     = 0x040;
306    static const Addr CTRL_CNTVOFF_LO_BASE = 0x080;
307    static const Addr CTRL_CNTVOFF_HI_BASE = 0x084;
308
309    static const Addr TIMER_CNTPCT_LO    = 0x000;
310    static const Addr TIMER_CNTPCT_HI    = 0x004;
311    static const Addr TIMER_CNTVCT_LO    = 0x008;
312    static const Addr TIMER_CNTVCT_HI    = 0x00C;
313    static const Addr TIMER_CNTFRQ       = 0x010;
314    static const Addr TIMER_CNTEL0ACR    = 0x014;
315    static const Addr TIMER_CNTVOFF_LO   = 0x018;
316    static const Addr TIMER_CNTVOFF_HI   = 0x01C;
317    static const Addr TIMER_CNTP_CVAL_LO = 0x020;
318    static const Addr TIMER_CNTP_CVAL_HI = 0x024;
319    static const Addr TIMER_CNTP_TVAL    = 0x028;
320    static const Addr TIMER_CNTP_CTL     = 0x02C;
321    static const Addr TIMER_CNTV_CVAL_LO = 0x030;
322    static const Addr TIMER_CNTV_CVAL_HI = 0x034;
323    static const Addr TIMER_CNTV_TVAL    = 0x038;
324    static const Addr TIMER_CNTV_CTL     = 0x03C;
325
326  protected: // Params
327    const AddrRange ctrlRange;
328    const AddrRange timerRange;
329    const AddrRangeList addrRanges;
330
331  protected:
332    /// System counter.
333    SystemCounter systemCounter;
334    ArchTimer physTimer;
335    ArchTimer virtTimer;
336};
337
338#endif // __DEV_ARM_GENERIC_TIMER_HH__
339