generic_timer.hh revision 10844 
1/*
2 * Copyright (c) 2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Giacomo Gabrielli
38 *          Andreas Sandberg
39 */
40
41#ifndef __DEV_ARM_GENERIC_TIMER_HH__
42#define __DEV_ARM_GENERIC_TIMER_HH__
43
44#include "arch/arm/isa_device.hh"
45#include "base/bitunion.hh"
46#include "dev/arm/base_gic.hh"
47#include "sim/core.hh"
48#include "sim/sim_object.hh"
49
50/// @file
51/// This module implements the global system counter and the local per-CPU
52/// architected timers as specified by the ARM Generic Timer extension (ARM
53/// ARM, Issue C, Chapter 17).
54
55class Checkpoint;
56class GenericTimerParams;
57
58/// Global system counter.  It is shared by the architected timers.
59/// @todo: implement memory-mapped controls
60class SystemCounter
61{
62  protected:
63    /// Counter frequency (as specified by CNTFRQ).
64    uint64_t _freq;
65    /// Cached copy of the counter period (inverse of the frequency).
66    Tick _period;
67    /// Tick when the counter was reset.
68    Tick _resetTick;
69
70    uint32_t _regCntkctl;
71
72  public:
73    SystemCounter();
74
75    /// Returns the current value of the physical counter.
76    uint64_t value() const
77    {
78        if (_freq == 0)
79            return 0;  // Counter is still off.
80        return (curTick() - _resetTick) / _period;
81    }
82
83    /// Returns the counter frequency.
84    uint64_t freq() const { return _freq; }
85    /// Sets the counter frequency.
86    /// @param freq frequency in Hz.
87    void setFreq(uint32_t freq);
88
89    /// Returns the counter period.
90    Tick period() const { return _period; }
91
92    void setKernelControl(uint32_t val) { _regCntkctl = val; }
93    uint32_t getKernelControl() { return _regCntkctl; }
94
95    void serialize(std::ostream &os) const;
96    void unserialize(Checkpoint *cp, const std::string &section);
97
98  private:
99    // Disable copying
100    SystemCounter(const SystemCounter &c);
101};
102
103/// Per-CPU architected timer.
104class ArchTimer
105{
106  public:
107    class Interrupt
108    {
109      public:
110        Interrupt(BaseGic &gic, unsigned irq)
111            : _gic(gic), _ppi(false), _irq(irq), _cpu(0) {}
112
113        Interrupt(BaseGic &gic, unsigned irq, unsigned cpu)
114            : _gic(gic), _ppi(true), _irq(irq), _cpu(cpu) {}
115
116        void send();
117        void clear();
118
119      private:
120        BaseGic &_gic;
121        const bool _ppi;
122        const unsigned _irq;
123        const unsigned _cpu;
124    };
125
126  protected:
127    /// Control register.
128    BitUnion32(ArchTimerCtrl)
129    Bitfield<0> enable;
130    Bitfield<1> imask;
131    Bitfield<2> istatus;
132    EndBitUnion(ArchTimerCtrl)
133
134    /// Name of this timer.
135    const std::string _name;
136
137    /// Pointer to parent class.
138    SimObject &_parent;
139
140    SystemCounter &_systemCounter;
141
142    Interrupt _interrupt;
143
144    /// Value of the control register ({CNTP/CNTHP/CNTV}_CTL).
145    ArchTimerCtrl _control;
146    /// Programmed limit value for the upcounter ({CNTP/CNTHP/CNTV}_CVAL).
147    uint64_t _counterLimit;
148
149    /**
150     * Timer settings or the offset has changed, re-evaluate
151     * trigger condition and raise interrupt if necessary.
152     */
153    void updateCounter();
154
155    /// Called when the upcounter reaches the programmed value.
156    void counterLimitReached();
157    EventWrapper<ArchTimer, &ArchTimer::counterLimitReached>
158    _counterLimitReachedEvent;
159
160  public:
161    ArchTimer(const std::string &name,
162              SimObject &parent,
163              SystemCounter &sysctr,
164              const Interrupt &interrupt);
165
166    /// Returns the timer name.
167    std::string name() const { return _name; }
168
169    /// Returns the CompareValue view of the timer.
170    uint64_t compareValue() const { return _counterLimit; }
171    /// Sets the CompareValue view of the timer.
172    void setCompareValue(uint64_t val);
173
174    /// Returns the TimerValue view of the timer.
175    uint32_t timerValue() const { return _counterLimit - value(); }
176    /// Sets the TimerValue view of the timer.
177    void setTimerValue(uint32_t val);
178
179    /// Sets the control register.
180    uint32_t control() const { return _control; }
181    void setControl(uint32_t val);
182
183    /// Returns the value of the counter which this timer relies on.
184    uint64_t value() const;
185
186    void serialize(std::ostream &os) const;
187    void unserialize(Checkpoint *cp, const std::string &section);
188
189  private:
190    // Disable copying
191    ArchTimer(const ArchTimer &t);
192};
193
194class GenericTimer : public SimObject
195{
196  public:
197    GenericTimer(GenericTimerParams *p);
198
199    void serialize(std::ostream &os) M5_ATTR_OVERRIDE;
200    void unserialize(Checkpoint *cp, const std::string &sec) M5_ATTR_OVERRIDE;
201
202  public:
203    void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val);
204    ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu);
205
206  protected:
207    struct CoreTimers {
208        CoreTimers(GenericTimer &parent, unsigned cpu,
209                   unsigned _irqPhys)
210            : irqPhys(*parent.gic, _irqPhys, cpu),
211              // This should really be phys_timerN, but we are stuck with
212              // arch_timer for backwards compatibility.
213              phys(csprintf("%s.arch_timer%d", parent.name(), cpu),
214                   parent, parent.systemCounter,
215                   irqPhys)
216        {}
217
218        ArchTimer::Interrupt irqPhys;
219        ArchTimer phys;
220
221      private:
222        // Disable copying
223        CoreTimers(const CoreTimers &c);
224    };
225
226    CoreTimers &getTimers(int cpu_id);
227    void createTimers(unsigned cpus);
228
229    /// System counter.
230    SystemCounter systemCounter;
231
232    /// Per-CPU physical architected timers.
233    std::vector<std::unique_ptr<CoreTimers>> timers;
234
235  protected: // Configuration
236    /// Pointer to the GIC, needed to trigger timer interrupts.
237    BaseGic *const gic;
238
239    /// Physical timer interrupt
240    const unsigned irqPhys;
241};
242
243class GenericTimerISA : public ArmISA::BaseISADevice
244{
245  public:
246    GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
247        : parent(_parent), cpu(_cpu) {}
248
249    void setMiscReg(int misc_reg, ArmISA::MiscReg val) M5_ATTR_OVERRIDE {
250        parent.setMiscReg(misc_reg, cpu, val);
251    }
252    ArmISA::MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE {
253        return parent.readMiscReg(misc_reg, cpu);
254    }
255
256  protected:
257    GenericTimer &parent;
258    unsigned cpu;
259};
260
261#endif // __DEV_ARM_GENERIC_TIMER_HH__
262