generic_timer.hh revision 12733
14479Sbinkertn@umich.edu/* 24479Sbinkertn@umich.edu * Copyright (c) 2013, 2015, 2017 ARM Limited 34479Sbinkertn@umich.edu * All rights reserved. 44479Sbinkertn@umich.edu * 54479Sbinkertn@umich.edu * The license below extends only to copyright in the software and shall 64479Sbinkertn@umich.edu * not be construed as granting a license to any other intellectual 74479Sbinkertn@umich.edu * property including but not limited to intellectual property relating 84479Sbinkertn@umich.edu * to a hardware implementation of the functionality of the software 94479Sbinkertn@umich.edu * licensed hereunder. You may use the software subject to the license 104479Sbinkertn@umich.edu * terms below provided that you ensure that this notice is replicated 114479Sbinkertn@umich.edu * unmodified and in its entirety in all distributions of the software, 124479Sbinkertn@umich.edu * modified or unmodified, in source code or in binary form. 134479Sbinkertn@umich.edu * 144479Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without 154479Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are 164479Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright 174479Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer; 184479Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright 194479Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the 204479Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution; 214479Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 224479Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from 234479Sbinkertn@umich.edu * this software without specific prior written permission. 244479Sbinkertn@umich.edu * 254479Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 264479Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 274479Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 286498Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 294479Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 304479Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 314479Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 324479Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 334479Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 344479Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 354479Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 364479Sbinkertn@umich.edu * 374479Sbinkertn@umich.edu * Authors: Giacomo Gabrielli 384479Sbinkertn@umich.edu * Andreas Sandberg 394479Sbinkertn@umich.edu */ 404479Sbinkertn@umich.edu 414479Sbinkertn@umich.edu#ifndef __DEV_ARM_GENERIC_TIMER_HH__ 424479Sbinkertn@umich.edu#define __DEV_ARM_GENERIC_TIMER_HH__ 434479Sbinkertn@umich.edu 446498Snate@binkert.org#include "arch/arm/isa_device.hh" 454479Sbinkertn@umich.edu#include "arch/arm/system.hh" 464479Sbinkertn@umich.edu#include "base/bitunion.hh" 474479Sbinkertn@umich.edu#include "dev/arm/base_gic.hh" 484479Sbinkertn@umich.edu#include "sim/core.hh" 494479Sbinkertn@umich.edu#include "sim/sim_object.hh" 504479Sbinkertn@umich.edu 514479Sbinkertn@umich.edu/// @file 524479Sbinkertn@umich.edu/// This module implements the global system counter and the local per-CPU 534479Sbinkertn@umich.edu/// architected timers as specified by the ARM Generic Timer extension (ARM 546498Snate@binkert.org/// ARM, Issue C, Chapter 17). 554479Sbinkertn@umich.edu 564479Sbinkertn@umich.educlass Checkpoint; 576498Snate@binkert.orgclass GenericTimerParams; 584479Sbinkertn@umich.educlass GenericTimerMemParams; 594479Sbinkertn@umich.edu 604479Sbinkertn@umich.edu/// Global system counter. It is shared by the architected timers. 614479Sbinkertn@umich.edu/// @todo: implement memory-mapped controls 624479Sbinkertn@umich.educlass SystemCounter : public Serializable 634479Sbinkertn@umich.edu{ 644479Sbinkertn@umich.edu protected: 656498Snate@binkert.org /// Counter frequency (as specified by CNTFRQ). 666498Snate@binkert.org uint64_t _freq; 676498Snate@binkert.org /// Cached copy of the counter period (inverse of the frequency). 686498Snate@binkert.org Tick _period; 694479Sbinkertn@umich.edu /// Tick when the counter was reset. 704479Sbinkertn@umich.edu Tick _resetTick; 714479Sbinkertn@umich.edu 724479Sbinkertn@umich.edu /// Kernel event stream control register 734479Sbinkertn@umich.edu uint32_t _regCntkctl; 744479Sbinkertn@umich.edu /// Hypervisor event stream control register 75 uint32_t _regCnthctl; 76 77 public: 78 SystemCounter(); 79 80 /// Returns the current value of the physical counter. 81 uint64_t value() const 82 { 83 if (_freq == 0) 84 return 0; // Counter is still off. 85 return (curTick() - _resetTick) / _period; 86 } 87 88 /// Returns the counter frequency. 89 uint64_t freq() const { return _freq; } 90 /// Sets the counter frequency. 91 /// @param freq frequency in Hz. 92 void setFreq(uint32_t freq); 93 94 /// Returns the counter period. 95 Tick period() const { return _period; } 96 97 void setKernelControl(uint32_t val) { _regCntkctl = val; } 98 uint32_t getKernelControl() { return _regCntkctl; } 99 100 void setHypControl(uint32_t val) { _regCnthctl = val; } 101 uint32_t getHypControl() { return _regCnthctl; } 102 103 void serialize(CheckpointOut &cp) const override; 104 void unserialize(CheckpointIn &cp) override; 105 106 private: 107 // Disable copying 108 SystemCounter(const SystemCounter &c); 109}; 110 111/// Per-CPU architected timer. 112class ArchTimer : public Serializable, public Drainable 113{ 114 public: 115 class Interrupt 116 { 117 public: 118 Interrupt(BaseGic &gic, unsigned irq) 119 : _gic(gic), _ppi(false), _irq(irq), _cpu(0) {} 120 121 Interrupt(BaseGic &gic, unsigned irq, unsigned cpu) 122 : _gic(gic), _ppi(true), _irq(irq), _cpu(cpu) {} 123 124 void send(); 125 void clear(); 126 127 private: 128 BaseGic &_gic; 129 const bool _ppi; 130 const unsigned _irq; 131 const unsigned _cpu; 132 }; 133 134 protected: 135 /// Control register. 136 BitUnion32(ArchTimerCtrl) 137 Bitfield<0> enable; 138 Bitfield<1> imask; 139 Bitfield<2> istatus; 140 EndBitUnion(ArchTimerCtrl) 141 142 /// Name of this timer. 143 const std::string _name; 144 145 /// Pointer to parent class. 146 SimObject &_parent; 147 148 SystemCounter &_systemCounter; 149 150 Interrupt _interrupt; 151 152 /// Value of the control register ({CNTP/CNTHP/CNTV}_CTL). 153 ArchTimerCtrl _control; 154 /// Programmed limit value for the upcounter ({CNTP/CNTHP/CNTV}_CVAL). 155 uint64_t _counterLimit; 156 /// Offset relative to the physical timer (CNTVOFF) 157 uint64_t _offset; 158 159 /** 160 * Timer settings or the offset has changed, re-evaluate 161 * trigger condition and raise interrupt if necessary. 162 */ 163 void updateCounter(); 164 165 /// Called when the upcounter reaches the programmed value. 166 void counterLimitReached(); 167 EventFunctionWrapper _counterLimitReachedEvent; 168 169 virtual bool scheduleEvents() { return true; } 170 171 public: 172 ArchTimer(const std::string &name, 173 SimObject &parent, 174 SystemCounter &sysctr, 175 const Interrupt &interrupt); 176 177 /// Returns the timer name. 178 std::string name() const { return _name; } 179 180 /// Returns the CompareValue view of the timer. 181 uint64_t compareValue() const { return _counterLimit; } 182 /// Sets the CompareValue view of the timer. 183 void setCompareValue(uint64_t val); 184 185 /// Returns the TimerValue view of the timer. 186 uint32_t timerValue() const { return _counterLimit - value(); } 187 /// Sets the TimerValue view of the timer. 188 void setTimerValue(uint32_t val); 189 190 /// Sets the control register. 191 uint32_t control() const { return _control; } 192 void setControl(uint32_t val); 193 194 uint64_t offset() const { return _offset; } 195 void setOffset(uint64_t val); 196 197 /// Returns the value of the counter which this timer relies on. 198 uint64_t value() const; 199 200 // Serializable 201 void serialize(CheckpointOut &cp) const override; 202 void unserialize(CheckpointIn &cp) override; 203 204 // Drainable 205 DrainState drain() override; 206 void drainResume() override; 207 208 private: 209 // Disable copying 210 ArchTimer(const ArchTimer &t); 211}; 212 213class ArchTimerKvm : public ArchTimer 214{ 215 private: 216 ArmSystem &system; 217 218 public: 219 ArchTimerKvm(const std::string &name, 220 ArmSystem &system, 221 SimObject &parent, 222 SystemCounter &sysctr, 223 const Interrupt &interrupt) 224 : ArchTimer(name, parent, sysctr, interrupt), system(system) {} 225 226 protected: 227 // For ArchTimer's in a GenericTimerISA with Kvm execution about 228 // to begin, skip rescheduling the event. 229 // Otherwise, we should reschedule the event (if necessary). 230 bool scheduleEvents() override { 231 return !system.validKvmEnvironment(); 232 } 233}; 234 235class GenericTimer : public ClockedObject 236{ 237 public: 238 GenericTimer(GenericTimerParams *p); 239 240 void serialize(CheckpointOut &cp) const override; 241 void unserialize(CheckpointIn &cp) override; 242 243 public: 244 void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val); 245 ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu); 246 247 protected: 248 struct CoreTimers { 249 CoreTimers(GenericTimer &parent, ArmSystem &system, unsigned cpu, 250 unsigned _irqPhysS, unsigned _irqPhysNS, 251 unsigned _irqVirt, unsigned _irqHyp) 252 : irqPhysS(*parent.gic, _irqPhysS, cpu), 253 irqPhysNS(*parent.gic, _irqPhysNS, cpu), 254 irqVirt(*parent.gic, _irqVirt, cpu), 255 irqHyp(*parent.gic, _irqHyp, cpu), 256 physS(csprintf("%s.phys_s_timer%d", parent.name(), cpu), 257 system, parent, parent.systemCounter, 258 irqPhysS), 259 // This should really be phys_timerN, but we are stuck with 260 // arch_timer for backwards compatibility. 261 physNS(csprintf("%s.arch_timer%d", parent.name(), cpu), 262 system, parent, parent.systemCounter, 263 irqPhysNS), 264 virt(csprintf("%s.virt_timer%d", parent.name(), cpu), 265 system, parent, parent.systemCounter, 266 irqVirt), 267 hyp(csprintf("%s.hyp_timer%d", parent.name(), cpu), 268 system, parent, parent.systemCounter, 269 irqHyp) 270 {} 271 272 ArchTimer::Interrupt irqPhysS; 273 ArchTimer::Interrupt irqPhysNS; 274 ArchTimer::Interrupt irqVirt; 275 ArchTimer::Interrupt irqHyp; 276 277 ArchTimerKvm physS; 278 ArchTimerKvm physNS; 279 ArchTimerKvm virt; 280 ArchTimerKvm hyp; 281 282 private: 283 // Disable copying 284 CoreTimers(const CoreTimers &c); 285 }; 286 287 CoreTimers &getTimers(int cpu_id); 288 void createTimers(unsigned cpus); 289 290 /// System counter. 291 SystemCounter systemCounter; 292 293 /// Per-CPU physical architected timers. 294 std::vector<std::unique_ptr<CoreTimers>> timers; 295 296 protected: // Configuration 297 /// ARM system containing this timer 298 ArmSystem &system; 299 300 /// Pointer to the GIC, needed to trigger timer interrupts. 301 BaseGic *const gic; 302 303 /// Physical timer interrupt (S) 304 const unsigned irqPhysS; 305 /// Physical timer interrupt (NS) 306 const unsigned irqPhysNS; 307 308 /// Virtual timer interrupt 309 const unsigned irqVirt; 310 311 /// Hypervisor timer interrupt 312 const unsigned irqHyp; 313}; 314 315class GenericTimerISA : public ArmISA::BaseISADevice 316{ 317 public: 318 GenericTimerISA(GenericTimer &_parent, unsigned _cpu) 319 : parent(_parent), cpu(_cpu) {} 320 321 void setMiscReg(int misc_reg, ArmISA::MiscReg val) override { 322 parent.setMiscReg(misc_reg, cpu, val); 323 } 324 ArmISA::MiscReg readMiscReg(int misc_reg) override { 325 return parent.readMiscReg(misc_reg, cpu); 326 } 327 328 protected: 329 GenericTimer &parent; 330 unsigned cpu; 331}; 332 333class GenericTimerMem : public PioDevice 334{ 335 public: 336 GenericTimerMem(GenericTimerMemParams *p); 337 338 void serialize(CheckpointOut &cp) const override; 339 void unserialize(CheckpointIn &cp) override; 340 341 public: // PioDevice 342 AddrRangeList getAddrRanges() const override { return addrRanges; } 343 Tick read(PacketPtr pkt) override; 344 Tick write(PacketPtr pkt) override; 345 346 protected: 347 uint64_t ctrlRead(Addr addr, size_t size) const; 348 void ctrlWrite(Addr addr, size_t size, uint64_t value); 349 350 uint64_t timerRead(Addr addr, size_t size) const; 351 void timerWrite(Addr addr, size_t size, uint64_t value); 352 353 protected: // Registers 354 static const Addr CTRL_CNTFRQ = 0x000; 355 static const Addr CTRL_CNTNSAR = 0x004; 356 static const Addr CTRL_CNTTIDR = 0x008; 357 static const Addr CTRL_CNTACR_BASE = 0x040; 358 static const Addr CTRL_CNTVOFF_LO_BASE = 0x080; 359 static const Addr CTRL_CNTVOFF_HI_BASE = 0x084; 360 361 static const Addr TIMER_CNTPCT_LO = 0x000; 362 static const Addr TIMER_CNTPCT_HI = 0x004; 363 static const Addr TIMER_CNTVCT_LO = 0x008; 364 static const Addr TIMER_CNTVCT_HI = 0x00C; 365 static const Addr TIMER_CNTFRQ = 0x010; 366 static const Addr TIMER_CNTEL0ACR = 0x014; 367 static const Addr TIMER_CNTVOFF_LO = 0x018; 368 static const Addr TIMER_CNTVOFF_HI = 0x01C; 369 static const Addr TIMER_CNTP_CVAL_LO = 0x020; 370 static const Addr TIMER_CNTP_CVAL_HI = 0x024; 371 static const Addr TIMER_CNTP_TVAL = 0x028; 372 static const Addr TIMER_CNTP_CTL = 0x02C; 373 static const Addr TIMER_CNTV_CVAL_LO = 0x030; 374 static const Addr TIMER_CNTV_CVAL_HI = 0x034; 375 static const Addr TIMER_CNTV_TVAL = 0x038; 376 static const Addr TIMER_CNTV_CTL = 0x03C; 377 378 protected: // Params 379 const AddrRange ctrlRange; 380 const AddrRange timerRange; 381 const AddrRangeList addrRanges; 382 383 protected: 384 /// System counter. 385 SystemCounter systemCounter; 386 ArchTimer physTimer; 387 ArchTimer virtTimer; 388}; 389 390#endif // __DEV_ARM_GENERIC_TIMER_HH__ 391