generic_timer.hh revision 10845
1/* 2 * Copyright (c) 2013, 2015 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Giacomo Gabrielli 38 * Andreas Sandberg 39 */ 40 41#ifndef __DEV_ARM_GENERIC_TIMER_HH__ 42#define __DEV_ARM_GENERIC_TIMER_HH__ 43 44#include "arch/arm/isa_device.hh" 45#include "base/bitunion.hh" 46#include "dev/arm/base_gic.hh" 47#include "sim/core.hh" 48#include "sim/sim_object.hh" 49 50/// @file 51/// This module implements the global system counter and the local per-CPU 52/// architected timers as specified by the ARM Generic Timer extension (ARM 53/// ARM, Issue C, Chapter 17). 54 55class Checkpoint; 56class GenericTimerParams; 57 58/// Global system counter. It is shared by the architected timers. 59/// @todo: implement memory-mapped controls 60class SystemCounter 61{ 62 protected: 63 /// Counter frequency (as specified by CNTFRQ). 64 uint64_t _freq; 65 /// Cached copy of the counter period (inverse of the frequency). 66 Tick _period; 67 /// Tick when the counter was reset. 68 Tick _resetTick; 69 70 uint32_t _regCntkctl; 71 72 public: 73 SystemCounter(); 74 75 /// Returns the current value of the physical counter. 76 uint64_t value() const 77 { 78 if (_freq == 0) 79 return 0; // Counter is still off. 80 return (curTick() - _resetTick) / _period; 81 } 82 83 /// Returns the counter frequency. 84 uint64_t freq() const { return _freq; } 85 /// Sets the counter frequency. 86 /// @param freq frequency in Hz. 87 void setFreq(uint32_t freq); 88 89 /// Returns the counter period. 90 Tick period() const { return _period; } 91 92 void setKernelControl(uint32_t val) { _regCntkctl = val; } 93 uint32_t getKernelControl() { return _regCntkctl; } 94 95 void serialize(std::ostream &os) const; 96 void unserialize(Checkpoint *cp, const std::string §ion); 97 98 private: 99 // Disable copying 100 SystemCounter(const SystemCounter &c); 101}; 102 103/// Per-CPU architected timer. 104class ArchTimer 105{ 106 public: 107 class Interrupt 108 { 109 public: 110 Interrupt(BaseGic &gic, unsigned irq) 111 : _gic(gic), _ppi(false), _irq(irq), _cpu(0) {} 112 113 Interrupt(BaseGic &gic, unsigned irq, unsigned cpu) 114 : _gic(gic), _ppi(true), _irq(irq), _cpu(cpu) {} 115 116 void send(); 117 void clear(); 118 119 private: 120 BaseGic &_gic; 121 const bool _ppi; 122 const unsigned _irq; 123 const unsigned _cpu; 124 }; 125 126 protected: 127 /// Control register. 128 BitUnion32(ArchTimerCtrl) 129 Bitfield<0> enable; 130 Bitfield<1> imask; 131 Bitfield<2> istatus; 132 EndBitUnion(ArchTimerCtrl) 133 134 /// Name of this timer. 135 const std::string _name; 136 137 /// Pointer to parent class. 138 SimObject &_parent; 139 140 SystemCounter &_systemCounter; 141 142 Interrupt _interrupt; 143 144 /// Value of the control register ({CNTP/CNTHP/CNTV}_CTL). 145 ArchTimerCtrl _control; 146 /// Programmed limit value for the upcounter ({CNTP/CNTHP/CNTV}_CVAL). 147 uint64_t _counterLimit; 148 /// Offset relative to the physical timer (CNTVOFF) 149 uint64_t _offset; 150 151 /** 152 * Timer settings or the offset has changed, re-evaluate 153 * trigger condition and raise interrupt if necessary. 154 */ 155 void updateCounter(); 156 157 /// Called when the upcounter reaches the programmed value. 158 void counterLimitReached(); 159 EventWrapper<ArchTimer, &ArchTimer::counterLimitReached> 160 _counterLimitReachedEvent; 161 162 public: 163 ArchTimer(const std::string &name, 164 SimObject &parent, 165 SystemCounter &sysctr, 166 const Interrupt &interrupt); 167 168 /// Returns the timer name. 169 std::string name() const { return _name; } 170 171 /// Returns the CompareValue view of the timer. 172 uint64_t compareValue() const { return _counterLimit; } 173 /// Sets the CompareValue view of the timer. 174 void setCompareValue(uint64_t val); 175 176 /// Returns the TimerValue view of the timer. 177 uint32_t timerValue() const { return _counterLimit - value(); } 178 /// Sets the TimerValue view of the timer. 179 void setTimerValue(uint32_t val); 180 181 /// Sets the control register. 182 uint32_t control() const { return _control; } 183 void setControl(uint32_t val); 184 185 uint64_t offset() const { return _offset; } 186 void setOffset(uint64_t val); 187 188 /// Returns the value of the counter which this timer relies on. 189 uint64_t value() const; 190 191 void serialize(std::ostream &os) const; 192 void unserialize(Checkpoint *cp, const std::string §ion); 193 194 private: 195 // Disable copying 196 ArchTimer(const ArchTimer &t); 197}; 198 199class GenericTimer : public SimObject 200{ 201 public: 202 GenericTimer(GenericTimerParams *p); 203 204 void serialize(std::ostream &os) M5_ATTR_OVERRIDE; 205 void unserialize(Checkpoint *cp, const std::string &sec) M5_ATTR_OVERRIDE; 206 207 public: 208 void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val); 209 ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu); 210 211 protected: 212 struct CoreTimers { 213 CoreTimers(GenericTimer &parent, unsigned cpu, 214 unsigned _irqPhys, unsigned _irqVirt) 215 : irqPhys(*parent.gic, _irqPhys, cpu), 216 irqVirt(*parent.gic, _irqVirt, cpu), 217 // This should really be phys_timerN, but we are stuck with 218 // arch_timer for backwards compatibility. 219 phys(csprintf("%s.arch_timer%d", parent.name(), cpu), 220 parent, parent.systemCounter, 221 irqPhys), 222 virt(csprintf("%s.virt_timer%d", parent.name(), cpu), 223 parent, parent.systemCounter, 224 irqVirt) 225 {} 226 227 ArchTimer::Interrupt irqPhys; 228 ArchTimer::Interrupt irqVirt; 229 230 ArchTimer phys; 231 ArchTimer virt; 232 233 private: 234 // Disable copying 235 CoreTimers(const CoreTimers &c); 236 }; 237 238 CoreTimers &getTimers(int cpu_id); 239 void createTimers(unsigned cpus); 240 241 /// System counter. 242 SystemCounter systemCounter; 243 244 /// Per-CPU physical architected timers. 245 std::vector<std::unique_ptr<CoreTimers>> timers; 246 247 protected: // Configuration 248 /// Pointer to the GIC, needed to trigger timer interrupts. 249 BaseGic *const gic; 250 251 /// Physical timer interrupt 252 const unsigned irqPhys; 253 254 /// Virtual timer interrupt 255 const unsigned irqVirt; 256}; 257 258class GenericTimerISA : public ArmISA::BaseISADevice 259{ 260 public: 261 GenericTimerISA(GenericTimer &_parent, unsigned _cpu) 262 : parent(_parent), cpu(_cpu) {} 263 264 void setMiscReg(int misc_reg, ArmISA::MiscReg val) M5_ATTR_OVERRIDE { 265 parent.setMiscReg(misc_reg, cpu, val); 266 } 267 ArmISA::MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE { 268 return parent.readMiscReg(misc_reg, cpu); 269 } 270 271 protected: 272 GenericTimer &parent; 273 unsigned cpu; 274}; 275 276#endif // __DEV_ARM_GENERIC_TIMER_HH__ 277