generic_timer.cc revision 11668:380375085863
1/* 2 * Copyright (c) 2013, 2015 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Giacomo Gabrielli 38 * Andreas Sandberg 39 */ 40 41#include "dev/arm/generic_timer.hh" 42 43#include "arch/arm/system.hh" 44#include "debug/Timer.hh" 45#include "dev/arm/base_gic.hh" 46#include "mem/packet_access.hh" 47#include "params/GenericTimer.hh" 48#include "params/GenericTimerMem.hh" 49 50SystemCounter::SystemCounter() 51 : _freq(0), _period(0), _resetTick(0), _regCntkctl(0) 52{ 53 setFreq(0x01800000); 54} 55 56void 57SystemCounter::setFreq(uint32_t freq) 58{ 59 if (_freq != 0) { 60 // Altering the frequency after boot shouldn't be done in practice. 61 warn_once("The frequency of the system counter has already been set"); 62 } 63 _freq = freq; 64 _period = (1.0 / freq) * SimClock::Frequency; 65 _resetTick = curTick(); 66} 67 68void 69SystemCounter::serialize(CheckpointOut &cp) const 70{ 71 SERIALIZE_SCALAR(_regCntkctl); 72 SERIALIZE_SCALAR(_freq); 73 SERIALIZE_SCALAR(_period); 74 SERIALIZE_SCALAR(_resetTick); 75} 76 77void 78SystemCounter::unserialize(CheckpointIn &cp) 79{ 80 // We didn't handle CNTKCTL in this class before, assume it's zero 81 // if it isn't present. 82 if (!UNSERIALIZE_OPT_SCALAR(_regCntkctl)) 83 _regCntkctl = 0; 84 UNSERIALIZE_SCALAR(_freq); 85 UNSERIALIZE_SCALAR(_period); 86 UNSERIALIZE_SCALAR(_resetTick); 87} 88 89 90 91ArchTimer::ArchTimer(const std::string &name, 92 SimObject &parent, 93 SystemCounter &sysctr, 94 const Interrupt &interrupt) 95 : _name(name), _parent(parent), _systemCounter(sysctr), 96 _interrupt(interrupt), 97 _control(0), _counterLimit(0), _offset(0), 98 _counterLimitReachedEvent(this) 99{ 100} 101 102void 103ArchTimer::counterLimitReached() 104{ 105 _control.istatus = 1; 106 107 if (!_control.enable) 108 return; 109 110 DPRINTF(Timer, "Counter limit reached\n"); 111 if (!_control.imask) { 112 DPRINTF(Timer, "Causing interrupt\n"); 113 _interrupt.send(); 114 } 115} 116 117void 118ArchTimer::updateCounter() 119{ 120 if (_counterLimitReachedEvent.scheduled()) 121 _parent.deschedule(_counterLimitReachedEvent); 122 if (value() >= _counterLimit) { 123 counterLimitReached(); 124 } else { 125 const auto period(_systemCounter.period()); 126 _control.istatus = 0; 127 _parent.schedule(_counterLimitReachedEvent, 128 curTick() + (_counterLimit - value()) * period); 129 } 130} 131 132void 133ArchTimer::setCompareValue(uint64_t val) 134{ 135 _counterLimit = val; 136 updateCounter(); 137} 138 139void 140ArchTimer::setTimerValue(uint32_t val) 141{ 142 setCompareValue(value() + sext<32>(val)); 143} 144 145void 146ArchTimer::setControl(uint32_t val) 147{ 148 ArchTimerCtrl new_ctl = val; 149 if ((new_ctl.enable && !new_ctl.imask) && 150 !(_control.enable && !_control.imask)) { 151 // Re-evalute the timer condition 152 if (_counterLimit >= value()) { 153 _control.istatus = 1; 154 155 DPRINTF(Timer, "Causing interrupt in control\n"); 156 //_interrupt.send(); 157 } 158 } 159 _control.enable = new_ctl.enable; 160 _control.imask = new_ctl.imask; 161} 162 163void 164ArchTimer::setOffset(uint64_t val) 165{ 166 _offset = val; 167 updateCounter(); 168} 169 170uint64_t 171ArchTimer::value() const 172{ 173 return _systemCounter.value() - _offset; 174} 175 176void 177ArchTimer::serialize(CheckpointOut &cp) const 178{ 179 paramOut(cp, "control_serial", _control); 180 SERIALIZE_SCALAR(_counterLimit); 181 SERIALIZE_SCALAR(_offset); 182 183 const bool event_scheduled(_counterLimitReachedEvent.scheduled()); 184 SERIALIZE_SCALAR(event_scheduled); 185 if (event_scheduled) { 186 const Tick event_time(_counterLimitReachedEvent.when()); 187 SERIALIZE_SCALAR(event_time); 188 } 189} 190 191void 192ArchTimer::unserialize(CheckpointIn &cp) 193{ 194 paramIn(cp, "control_serial", _control); 195 // We didn't serialize an offset before we added support for the 196 // virtual timer. Consider it optional to maintain backwards 197 // compatibility. 198 if (!UNSERIALIZE_OPT_SCALAR(_offset)) 199 _offset = 0; 200 bool event_scheduled; 201 UNSERIALIZE_SCALAR(event_scheduled); 202 if (event_scheduled) { 203 Tick event_time; 204 UNSERIALIZE_SCALAR(event_time); 205 _parent.schedule(_counterLimitReachedEvent, event_time); 206 } 207} 208 209void 210ArchTimer::Interrupt::send() 211{ 212 if (_ppi) { 213 _gic.sendPPInt(_irq, _cpu); 214 } else { 215 _gic.sendInt(_irq); 216 } 217} 218 219 220void 221ArchTimer::Interrupt::clear() 222{ 223 if (_ppi) { 224 _gic.clearPPInt(_irq, _cpu); 225 } else { 226 _gic.clearInt(_irq); 227 } 228} 229 230 231GenericTimer::GenericTimer(GenericTimerParams *p) 232 : SimObject(p), 233 gic(p->gic), 234 irqPhys(p->int_phys), 235 irqVirt(p->int_virt) 236{ 237 fatal_if(!p->system, "No system specified, can't instantiate timer.\n"); 238 p->system->setGenericTimer(this); 239} 240 241void 242GenericTimer::serialize(CheckpointOut &cp) const 243{ 244 paramOut(cp, "cpu_count", timers.size()); 245 246 systemCounter.serializeSection(cp, "sys_counter"); 247 248 for (int i = 0; i < timers.size(); ++i) { 249 const CoreTimers &core(*timers[i]); 250 251 // This should really be phys_timerN, but we are stuck with 252 // arch_timer for backwards compatibility. 253 core.phys.serializeSection(cp, csprintf("arch_timer%d", i)); 254 core.virt.serializeSection(cp, csprintf("virt_timer%d", i)); 255 } 256} 257 258void 259GenericTimer::unserialize(CheckpointIn &cp) 260{ 261 systemCounter.unserializeSection(cp, "sys_counter"); 262 263 // Try to unserialize the CPU count. Old versions of the timer 264 // model assumed a 8 CPUs, so we fall back to that if the field 265 // isn't present. 266 static const unsigned OLD_CPU_MAX = 8; 267 unsigned cpu_count; 268 if (!UNSERIALIZE_OPT_SCALAR(cpu_count)) { 269 warn("Checkpoint does not contain CPU count, assuming %i CPUs\n", 270 OLD_CPU_MAX); 271 cpu_count = OLD_CPU_MAX; 272 } 273 274 for (int i = 0; i < cpu_count; ++i) { 275 CoreTimers &core(getTimers(i)); 276 // This should really be phys_timerN, but we are stuck with 277 // arch_timer for backwards compatibility. 278 core.phys.unserializeSection(cp, csprintf("arch_timer%d", i)); 279 core.virt.unserializeSection(cp, csprintf("virt_timer%d", i)); 280 } 281} 282 283 284GenericTimer::CoreTimers & 285GenericTimer::getTimers(int cpu_id) 286{ 287 if (cpu_id >= timers.size()) 288 createTimers(cpu_id + 1); 289 290 return *timers[cpu_id]; 291} 292 293void 294GenericTimer::createTimers(unsigned cpus) 295{ 296 assert(timers.size() < cpus); 297 298 const unsigned old_cpu_count(timers.size()); 299 timers.resize(cpus); 300 for (unsigned i = old_cpu_count; i < cpus; ++i) { 301 timers[i].reset( 302 new CoreTimers(*this, i, irqPhys, irqVirt)); 303 } 304} 305 306 307void 308GenericTimer::setMiscReg(int reg, unsigned cpu, MiscReg val) 309{ 310 CoreTimers &core(getTimers(cpu)); 311 312 switch (reg) { 313 case MISCREG_CNTFRQ: 314 case MISCREG_CNTFRQ_EL0: 315 systemCounter.setFreq(val); 316 return; 317 318 case MISCREG_CNTKCTL: 319 case MISCREG_CNTKCTL_EL1: 320 systemCounter.setKernelControl(val); 321 return; 322 323 // Physical timer 324 case MISCREG_CNTP_CVAL: 325 case MISCREG_CNTP_CVAL_NS: 326 case MISCREG_CNTP_CVAL_EL0: 327 core.phys.setCompareValue(val); 328 return; 329 330 case MISCREG_CNTP_TVAL: 331 case MISCREG_CNTP_TVAL_NS: 332 case MISCREG_CNTP_TVAL_EL0: 333 core.phys.setTimerValue(val); 334 return; 335 336 case MISCREG_CNTP_CTL: 337 case MISCREG_CNTP_CTL_NS: 338 case MISCREG_CNTP_CTL_EL0: 339 core.phys.setControl(val); 340 return; 341 342 // Count registers 343 case MISCREG_CNTPCT: 344 case MISCREG_CNTPCT_EL0: 345 case MISCREG_CNTVCT: 346 case MISCREG_CNTVCT_EL0: 347 warn("Ignoring write to read only count register: %s\n", 348 miscRegName[reg]); 349 return; 350 351 // Virtual timer 352 case MISCREG_CNTVOFF: 353 case MISCREG_CNTVOFF_EL2: 354 core.virt.setOffset(val); 355 return; 356 357 case MISCREG_CNTV_CVAL: 358 case MISCREG_CNTV_CVAL_EL0: 359 core.virt.setCompareValue(val); 360 return; 361 362 case MISCREG_CNTV_TVAL: 363 case MISCREG_CNTV_TVAL_EL0: 364 core.virt.setTimerValue(val); 365 return; 366 367 case MISCREG_CNTV_CTL: 368 case MISCREG_CNTV_CTL_EL0: 369 core.virt.setControl(val); 370 return; 371 372 // PL1 phys. timer, secure 373 case MISCREG_CNTP_CTL_S: 374 case MISCREG_CNTPS_CVAL_EL1: 375 case MISCREG_CNTPS_TVAL_EL1: 376 case MISCREG_CNTPS_CTL_EL1: 377 /* FALLTHROUGH */ 378 379 // PL2 phys. timer, non-secure 380 case MISCREG_CNTHCTL: 381 case MISCREG_CNTHCTL_EL2: 382 case MISCREG_CNTHP_CVAL: 383 case MISCREG_CNTHP_CVAL_EL2: 384 case MISCREG_CNTHP_TVAL: 385 case MISCREG_CNTHP_TVAL_EL2: 386 case MISCREG_CNTHP_CTL: 387 case MISCREG_CNTHP_CTL_EL2: 388 warn("Writing to unimplemented register: %s\n", 389 miscRegName[reg]); 390 return; 391 392 default: 393 warn("Writing to unknown register: %s\n", miscRegName[reg]); 394 return; 395 } 396} 397 398 399MiscReg 400GenericTimer::readMiscReg(int reg, unsigned cpu) 401{ 402 CoreTimers &core(getTimers(cpu)); 403 404 switch (reg) { 405 case MISCREG_CNTFRQ: 406 case MISCREG_CNTFRQ_EL0: 407 return systemCounter.freq(); 408 409 case MISCREG_CNTKCTL: 410 case MISCREG_CNTKCTL_EL1: 411 return systemCounter.getKernelControl(); 412 413 // Physical timer 414 case MISCREG_CNTP_CVAL: 415 case MISCREG_CNTP_CVAL_EL0: 416 return core.phys.compareValue(); 417 418 case MISCREG_CNTP_TVAL: 419 case MISCREG_CNTP_TVAL_EL0: 420 return core.phys.timerValue(); 421 422 case MISCREG_CNTP_CTL: 423 case MISCREG_CNTP_CTL_EL0: 424 case MISCREG_CNTP_CTL_NS: 425 return core.phys.control(); 426 427 case MISCREG_CNTPCT: 428 case MISCREG_CNTPCT_EL0: 429 return core.phys.value(); 430 431 432 // Virtual timer 433 case MISCREG_CNTVCT: 434 case MISCREG_CNTVCT_EL0: 435 return core.virt.value(); 436 437 case MISCREG_CNTVOFF: 438 case MISCREG_CNTVOFF_EL2: 439 return core.virt.offset(); 440 441 case MISCREG_CNTV_CVAL: 442 case MISCREG_CNTV_CVAL_EL0: 443 return core.virt.compareValue(); 444 445 case MISCREG_CNTV_TVAL: 446 case MISCREG_CNTV_TVAL_EL0: 447 return core.virt.timerValue(); 448 449 case MISCREG_CNTV_CTL: 450 case MISCREG_CNTV_CTL_EL0: 451 return core.virt.control(); 452 453 // PL1 phys. timer, secure 454 case MISCREG_CNTP_CTL_S: 455 case MISCREG_CNTPS_CVAL_EL1: 456 case MISCREG_CNTPS_TVAL_EL1: 457 case MISCREG_CNTPS_CTL_EL1: 458 /* FALLTHROUGH */ 459 460 // PL2 phys. timer, non-secure 461 case MISCREG_CNTHCTL: 462 case MISCREG_CNTHCTL_EL2: 463 case MISCREG_CNTHP_CVAL: 464 case MISCREG_CNTHP_CVAL_EL2: 465 case MISCREG_CNTHP_TVAL: 466 case MISCREG_CNTHP_TVAL_EL2: 467 case MISCREG_CNTHP_CTL: 468 case MISCREG_CNTHP_CTL_EL2: 469 warn("Reading from unimplemented register: %s\n", 470 miscRegName[reg]); 471 return 0; 472 473 474 default: 475 warn("Reading from unknown register: %s\n", miscRegName[reg]); 476 return 0; 477 } 478} 479 480 481 482GenericTimerMem::GenericTimerMem(GenericTimerMemParams *p) 483 : PioDevice(p), 484 ctrlRange(RangeSize(p->base, TheISA::PageBytes)), 485 timerRange(RangeSize(p->base + TheISA::PageBytes, TheISA::PageBytes)), 486 addrRanges{ctrlRange, timerRange}, 487 systemCounter(), 488 physTimer(csprintf("%s.phys_timer0", name()), 489 *this, systemCounter, 490 ArchTimer::Interrupt(*p->gic, p->int_phys)), 491 virtTimer(csprintf("%s.virt_timer0", name()), 492 *this, systemCounter, 493 ArchTimer::Interrupt(*p->gic, p->int_virt)) 494{ 495} 496 497void 498GenericTimerMem::serialize(CheckpointOut &cp) const 499{ 500 paramOut(cp, "timer_count", 1); 501 502 systemCounter.serializeSection(cp, "sys_counter"); 503 504 physTimer.serializeSection(cp, "phys_timer0"); 505 virtTimer.serializeSection(cp, "virt_timer0"); 506} 507 508void 509GenericTimerMem::unserialize(CheckpointIn &cp) 510{ 511 systemCounter.unserializeSection(cp, "sys_counter"); 512 513 unsigned timer_count; 514 UNSERIALIZE_SCALAR(timer_count); 515 // The timer count variable is just here for future versions where 516 // we support more than one set of timers. 517 if (timer_count != 1) 518 panic("Incompatible checkpoint: Only one set of timers supported"); 519 520 physTimer.unserializeSection(cp, "phys_timer0"); 521 virtTimer.unserializeSection(cp, "virt_timer0"); 522} 523 524Tick 525GenericTimerMem::read(PacketPtr pkt) 526{ 527 const unsigned size(pkt->getSize()); 528 const Addr addr(pkt->getAddr()); 529 uint64_t value; 530 531 pkt->makeResponse(); 532 if (ctrlRange.contains(addr)) { 533 value = ctrlRead(addr - ctrlRange.start(), size); 534 } else if (timerRange.contains(addr)) { 535 value = timerRead(addr - timerRange.start(), size); 536 } else { 537 panic("Invalid address: 0x%x\n", addr); 538 } 539 540 DPRINTF(Timer, "Read 0x%x <- 0x%x(%i)\n", value, addr, size); 541 542 if (size == 8) { 543 pkt->set<uint64_t>(value); 544 } else if (size == 4) { 545 pkt->set<uint32_t>(value); 546 } else { 547 panic("Unexpected access size: %i\n", size); 548 } 549 550 return 0; 551} 552 553Tick 554GenericTimerMem::write(PacketPtr pkt) 555{ 556 const unsigned size(pkt->getSize()); 557 if (size != 8 && size != 4) 558 panic("Unexpected access size\n"); 559 560 const Addr addr(pkt->getAddr()); 561 const uint64_t value(size == 8 ? 562 pkt->get<uint64_t>() : pkt->get<uint32_t>()); 563 564 DPRINTF(Timer, "Write 0x%x -> 0x%x(%i)\n", value, addr, size); 565 if (ctrlRange.contains(addr)) { 566 ctrlWrite(addr - ctrlRange.start(), size, value); 567 } else if (timerRange.contains(addr)) { 568 timerWrite(addr - timerRange.start(), size, value); 569 } else { 570 panic("Invalid address: 0x%x\n", addr); 571 } 572 573 pkt->makeResponse(); 574 return 0; 575} 576 577uint64_t 578GenericTimerMem::ctrlRead(Addr addr, size_t size) const 579{ 580 if (size == 4) { 581 switch (addr) { 582 case CTRL_CNTFRQ: 583 return systemCounter.freq(); 584 585 case CTRL_CNTTIDR: 586 return 0x3; // Frame 0 implemented with virtual timers 587 588 case CTRL_CNTNSAR: 589 case CTRL_CNTACR_BASE: 590 warn("Reading from unimplemented control register (0x%x)\n", addr); 591 return 0; 592 593 case CTRL_CNTVOFF_LO_BASE: 594 return virtTimer.offset(); 595 596 case CTRL_CNTVOFF_HI_BASE: 597 return virtTimer.offset() >> 32; 598 599 default: 600 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr, size); 601 return 0; 602 } 603 } else if (size == 8) { 604 switch (addr) { 605 case CTRL_CNTVOFF_LO_BASE: 606 return virtTimer.offset(); 607 608 default: 609 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr, size); 610 return 0; 611 } 612 } else { 613 panic("Invalid access size: %i\n", size); 614 } 615} 616 617void 618GenericTimerMem::ctrlWrite(Addr addr, size_t size, uint64_t value) 619{ 620 if (size == 4) { 621 switch (addr) { 622 case CTRL_CNTFRQ: 623 case CTRL_CNTNSAR: 624 case CTRL_CNTTIDR: 625 case CTRL_CNTACR_BASE: 626 warn("Write to unimplemented control register (0x%x)\n", addr); 627 return; 628 629 case CTRL_CNTVOFF_LO_BASE: 630 virtTimer.setOffset( 631 insertBits(virtTimer.offset(), 31, 0, value)); 632 return; 633 634 case CTRL_CNTVOFF_HI_BASE: 635 virtTimer.setOffset( 636 insertBits(virtTimer.offset(), 63, 32, value)); 637 return; 638 639 default: 640 warn("Ignoring write to unexpected address (0x%x:%i)\n", 641 addr, size); 642 return; 643 } 644 } else if (size == 8) { 645 switch (addr) { 646 case CTRL_CNTVOFF_LO_BASE: 647 virtTimer.setOffset(value); 648 return; 649 650 default: 651 warn("Ignoring write to unexpected address (0x%x:%i)\n", 652 addr, size); 653 return; 654 } 655 } else { 656 panic("Invalid access size: %i\n", size); 657 } 658} 659 660uint64_t 661GenericTimerMem::timerRead(Addr addr, size_t size) const 662{ 663 if (size == 4) { 664 switch (addr) { 665 case TIMER_CNTPCT_LO: 666 return physTimer.value(); 667 668 case TIMER_CNTPCT_HI: 669 return physTimer.value() >> 32; 670 671 case TIMER_CNTVCT_LO: 672 return virtTimer.value(); 673 674 case TIMER_CNTVCT_HI: 675 return virtTimer.value() >> 32; 676 677 case TIMER_CNTFRQ: 678 return systemCounter.freq(); 679 680 case TIMER_CNTEL0ACR: 681 warn("Read from unimplemented timer register (0x%x)\n", addr); 682 return 0; 683 684 case CTRL_CNTVOFF_LO_BASE: 685 return virtTimer.offset(); 686 687 case CTRL_CNTVOFF_HI_BASE: 688 return virtTimer.offset() >> 32; 689 690 case TIMER_CNTP_CVAL_LO: 691 return physTimer.compareValue(); 692 693 case TIMER_CNTP_CVAL_HI: 694 return physTimer.compareValue() >> 32; 695 696 case TIMER_CNTP_TVAL: 697 return physTimer.timerValue(); 698 699 case TIMER_CNTP_CTL: 700 return physTimer.control(); 701 702 case TIMER_CNTV_CVAL_LO: 703 return virtTimer.compareValue(); 704 705 case TIMER_CNTV_CVAL_HI: 706 return virtTimer.compareValue() >> 32; 707 708 case TIMER_CNTV_TVAL: 709 return virtTimer.timerValue(); 710 711 case TIMER_CNTV_CTL: 712 return virtTimer.control(); 713 714 default: 715 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr, size); 716 return 0; 717 } 718 } else if (size == 8) { 719 switch (addr) { 720 case TIMER_CNTPCT_LO: 721 return physTimer.value(); 722 723 case TIMER_CNTVCT_LO: 724 return virtTimer.value(); 725 726 case CTRL_CNTVOFF_LO_BASE: 727 return virtTimer.offset(); 728 729 case TIMER_CNTP_CVAL_LO: 730 return physTimer.compareValue(); 731 732 case TIMER_CNTV_CVAL_LO: 733 return virtTimer.compareValue(); 734 735 default: 736 warn("Unexpected address (0x%x:%i), assuming RAZ\n", addr, size); 737 return 0; 738 } 739 } else { 740 panic("Invalid access size: %i\n", size); 741 } 742} 743 744void 745GenericTimerMem::timerWrite(Addr addr, size_t size, uint64_t value) 746{ 747 if (size == 4) { 748 switch (addr) { 749 case TIMER_CNTEL0ACR: 750 warn("Unimplemented timer register (0x%x)\n", addr); 751 return; 752 753 case TIMER_CNTP_CVAL_LO: 754 physTimer.setCompareValue( 755 insertBits(physTimer.compareValue(), 31, 0, value)); 756 return; 757 758 case TIMER_CNTP_CVAL_HI: 759 physTimer.setCompareValue( 760 insertBits(physTimer.compareValue(), 63, 32, value)); 761 return; 762 763 case TIMER_CNTP_TVAL: 764 physTimer.setTimerValue(value); 765 return; 766 767 case TIMER_CNTP_CTL: 768 physTimer.setControl(value); 769 return; 770 771 case TIMER_CNTV_CVAL_LO: 772 virtTimer.setCompareValue( 773 insertBits(virtTimer.compareValue(), 31, 0, value)); 774 return; 775 776 case TIMER_CNTV_CVAL_HI: 777 virtTimer.setCompareValue( 778 insertBits(virtTimer.compareValue(), 63, 32, value)); 779 return; 780 781 case TIMER_CNTV_TVAL: 782 virtTimer.setTimerValue(value); 783 return; 784 785 case TIMER_CNTV_CTL: 786 virtTimer.setControl(value); 787 return; 788 789 default: 790 warn("Unexpected address (0x%x:%i), ignoring write\n", addr, size); 791 return; 792 } 793 } else if (size == 8) { 794 switch (addr) { 795 case TIMER_CNTP_CVAL_LO: 796 return physTimer.setCompareValue(value); 797 798 case TIMER_CNTV_CVAL_LO: 799 return virtTimer.setCompareValue(value); 800 801 default: 802 warn("Unexpected address (0x%x:%i), ignoring write\n", addr, size); 803 return; 804 } 805 } else { 806 panic("Invalid access size: %i\n", size); 807 } 808} 809 810GenericTimer * 811GenericTimerParams::create() 812{ 813 return new GenericTimer(this); 814} 815 816GenericTimerMem * 817GenericTimerMemParams::create() 818{ 819 return new GenericTimerMem(this); 820} 821