base_gic.hh revision 11943 
1/*
2 * Copyright (c) 2012-2013, 2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 */
39
40/** @file
41 * Base class for ARM GIC implementations
42 */
43
44#ifndef __DEV_ARM_BASE_GIC_H__
45#define __DEV_ARM_BASE_GIC_H__
46
47#include "dev/io_device.hh"
48
49class Platform;
50
51class BaseGic :  public PioDevice
52{
53  public:
54    typedef struct BaseGicParams Params;
55
56    BaseGic(const Params *p);
57    virtual ~BaseGic();
58
59    const Params * params() const;
60
61    /**
62     * Post an interrupt from a device that is connected to the GIC.
63     *
64     * Depending on the configuration, the GIC will pass this interrupt
65     * on through to a CPU.
66     *
67     * @param num number of interrupt to send
68     */
69    virtual void sendInt(uint32_t num) = 0;
70
71    /**
72     * Interface call for private peripheral interrupts.
73     *
74     * @param num number of interrupt to send
75     * @param cpu CPU to forward interrupt to
76     */
77    virtual void sendPPInt(uint32_t num, uint32_t cpu) = 0;
78    virtual void clearPPInt(uint32_t num, uint32_t cpu) = 0;
79
80    /**
81     * Clear an interrupt from a device that is connected to the GIC.
82     *
83     * Depending on the configuration, the GIC may de-assert it's CPU
84     * line.
85     *
86     * @param num number of interrupt to send
87     */
88    virtual void clearInt(uint32_t num) = 0;
89
90  protected:
91    /** Platform this GIC belongs to. */
92    Platform *platform;
93};
94
95class BaseGicRegisters
96{
97  public:
98    virtual uint32_t readDistributor(ContextID ctx, Addr daddr) = 0;
99    virtual uint32_t readCpu(ContextID ctx, Addr daddr) = 0;
100
101    virtual void writeDistributor(ContextID ctx, Addr daddr,
102                                  uint32_t data) = 0;
103    virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data) = 0;
104};
105
106#endif
107