base_gic.hh revision 12970 
1/*
2 * Copyright (c) 2012-2013, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 */
39
40/** @file
41 * Base class for ARM GIC implementations
42 */
43
44#ifndef __DEV_ARM_BASE_GIC_H__
45#define __DEV_ARM_BASE_GIC_H__
46
47#include "dev/io_device.hh"
48
49class Platform;
50class RealView;
51class ThreadContext;
52
53struct ArmInterruptPinParams;
54struct ArmPPIParams;
55struct ArmSPIParams;
56struct BaseGicParams;
57
58class BaseGic :  public PioDevice
59{
60  public:
61    typedef BaseGicParams Params;
62
63    BaseGic(const Params *p);
64    virtual ~BaseGic();
65
66    const Params * params() const;
67
68    /**
69     * Post an interrupt from a device that is connected to the GIC.
70     *
71     * Depending on the configuration, the GIC will pass this interrupt
72     * on through to a CPU.
73     *
74     * @param num number of interrupt to send
75     */
76    virtual void sendInt(uint32_t num) = 0;
77
78    /**
79     * Interface call for private peripheral interrupts.
80     *
81     * @param num number of interrupt to send
82     * @param cpu CPU to forward interrupt to
83     */
84    virtual void sendPPInt(uint32_t num, uint32_t cpu) = 0;
85    virtual void clearPPInt(uint32_t num, uint32_t cpu) = 0;
86
87    /**
88     * Clear an interrupt from a device that is connected to the GIC.
89     *
90     * Depending on the configuration, the GIC may de-assert it's CPU
91     * line.
92     *
93     * @param num number of interrupt to send
94     */
95    virtual void clearInt(uint32_t num) = 0;
96
97  protected:
98    /** Platform this GIC belongs to. */
99    Platform *platform;
100};
101
102class BaseGicRegisters
103{
104  public:
105    virtual uint32_t readDistributor(ContextID ctx, Addr daddr) = 0;
106    virtual uint32_t readCpu(ContextID ctx, Addr daddr) = 0;
107
108    virtual void writeDistributor(ContextID ctx, Addr daddr,
109                                  uint32_t data) = 0;
110    virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data) = 0;
111};
112
113/**
114 * Generic representation of an Arm interrupt pin.
115 */
116class ArmInterruptPin : public SimObject
117{
118  public:
119    ArmInterruptPin(const ArmInterruptPinParams *p);
120
121  public: /* Public interface */
122    /**
123     * Set the thread context owning this interrupt.
124     *
125     * This method is used to set the thread context for interrupts
126     * that are thread/CPU-specific. Only devices that are used in
127     * such a context are expected to call this method.
128     */
129    void setThreadContext(ThreadContext *tc);
130
131    /** Get interrupt number */
132    uint32_t num() const { return intNum; }
133
134    /** Signal an interrupt */
135    virtual void raise() = 0;
136    /** Clear a signalled interrupt */
137    virtual void clear() = 0;
138
139  protected:
140    /**
141     * Get the target context ID of this interrupt.
142     *
143     * @pre setThreadContext() must have been called prior to calling
144     * this method.
145     */
146    ContextID targetContext() const;
147
148    /**
149     * Pointer to the thread context that owns this interrupt in case
150     * it is a thread-/CPU-private interrupt
151     */
152    const ThreadContext *threadContext;
153
154    /** Arm platform to use for interrupt generation */
155    RealView *const platform;
156    /** Interrupt number to generate */
157    const uint32_t intNum;
158};
159
160class ArmSPI : public ArmInterruptPin
161{
162  public:
163    ArmSPI(const ArmSPIParams *p);
164
165    void raise() override;
166    void clear() override;
167};
168
169class ArmPPI : public ArmInterruptPin
170{
171  public:
172    ArmPPI(const ArmPPIParams *p);
173
174    void raise() override;
175    void clear() override;
176};
177
178
179#endif
180