base_gic.hh revision 12739
19525SAndreas.Sandberg@ARM.com/* 212739Sandreas.sandberg@arm.com * Copyright (c) 2012-2013, 2017-2018 ARM Limited 39525SAndreas.Sandberg@ARM.com * All rights reserved 49525SAndreas.Sandberg@ARM.com * 59525SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69525SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79525SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89525SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99525SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109525SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119525SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129525SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139525SAndreas.Sandberg@ARM.com * 149525SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without 159525SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are 169525SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright 179525SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer; 189525SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright 199525SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the 209525SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution; 219525SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its 229525SAndreas.Sandberg@ARM.com * contributors may be used to endorse or promote products derived from 239525SAndreas.Sandberg@ARM.com * this software without specific prior written permission. 249525SAndreas.Sandberg@ARM.com * 259525SAndreas.Sandberg@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 269525SAndreas.Sandberg@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 279525SAndreas.Sandberg@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 289525SAndreas.Sandberg@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 299525SAndreas.Sandberg@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 309525SAndreas.Sandberg@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 319525SAndreas.Sandberg@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 329525SAndreas.Sandberg@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 339525SAndreas.Sandberg@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 349525SAndreas.Sandberg@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 359525SAndreas.Sandberg@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 369525SAndreas.Sandberg@ARM.com * 379525SAndreas.Sandberg@ARM.com * Authors: Andreas Sandberg 389525SAndreas.Sandberg@ARM.com */ 399525SAndreas.Sandberg@ARM.com 409525SAndreas.Sandberg@ARM.com/** @file 419525SAndreas.Sandberg@ARM.com * Base class for ARM GIC implementations 429525SAndreas.Sandberg@ARM.com */ 439525SAndreas.Sandberg@ARM.com 449525SAndreas.Sandberg@ARM.com#ifndef __DEV_ARM_BASE_GIC_H__ 459525SAndreas.Sandberg@ARM.com#define __DEV_ARM_BASE_GIC_H__ 469525SAndreas.Sandberg@ARM.com 479525SAndreas.Sandberg@ARM.com#include "dev/io_device.hh" 489525SAndreas.Sandberg@ARM.com 499525SAndreas.Sandberg@ARM.comclass Platform; 5012739Sandreas.sandberg@arm.comclass RealView; 5112739Sandreas.sandberg@arm.comclass ThreadContext; 5212739Sandreas.sandberg@arm.com 5312739Sandreas.sandberg@arm.comstruct ArmInterruptPinParams; 5412739Sandreas.sandberg@arm.comstruct ArmPPIParams; 5512739Sandreas.sandberg@arm.comstruct ArmSPIParams; 5612739Sandreas.sandberg@arm.comstruct BaseGicParams; 579525SAndreas.Sandberg@ARM.com 589525SAndreas.Sandberg@ARM.comclass BaseGic : public PioDevice 599525SAndreas.Sandberg@ARM.com{ 609525SAndreas.Sandberg@ARM.com public: 6112739Sandreas.sandberg@arm.com typedef BaseGicParams Params; 629525SAndreas.Sandberg@ARM.com 639525SAndreas.Sandberg@ARM.com BaseGic(const Params *p); 649525SAndreas.Sandberg@ARM.com virtual ~BaseGic(); 659525SAndreas.Sandberg@ARM.com 669525SAndreas.Sandberg@ARM.com const Params * params() const; 679525SAndreas.Sandberg@ARM.com 689525SAndreas.Sandberg@ARM.com /** 699525SAndreas.Sandberg@ARM.com * Post an interrupt from a device that is connected to the GIC. 709525SAndreas.Sandberg@ARM.com * 719525SAndreas.Sandberg@ARM.com * Depending on the configuration, the GIC will pass this interrupt 729525SAndreas.Sandberg@ARM.com * on through to a CPU. 739525SAndreas.Sandberg@ARM.com * 749525SAndreas.Sandberg@ARM.com * @param num number of interrupt to send 759525SAndreas.Sandberg@ARM.com */ 769525SAndreas.Sandberg@ARM.com virtual void sendInt(uint32_t num) = 0; 779525SAndreas.Sandberg@ARM.com 789525SAndreas.Sandberg@ARM.com /** 799525SAndreas.Sandberg@ARM.com * Interface call for private peripheral interrupts. 809525SAndreas.Sandberg@ARM.com * 819525SAndreas.Sandberg@ARM.com * @param num number of interrupt to send 829525SAndreas.Sandberg@ARM.com * @param cpu CPU to forward interrupt to 839525SAndreas.Sandberg@ARM.com */ 849525SAndreas.Sandberg@ARM.com virtual void sendPPInt(uint32_t num, uint32_t cpu) = 0; 859942Smatt.evans@arm.com virtual void clearPPInt(uint32_t num, uint32_t cpu) = 0; 869525SAndreas.Sandberg@ARM.com 879525SAndreas.Sandberg@ARM.com /** 889525SAndreas.Sandberg@ARM.com * Clear an interrupt from a device that is connected to the GIC. 899525SAndreas.Sandberg@ARM.com * 909525SAndreas.Sandberg@ARM.com * Depending on the configuration, the GIC may de-assert it's CPU 919525SAndreas.Sandberg@ARM.com * line. 929525SAndreas.Sandberg@ARM.com * 939525SAndreas.Sandberg@ARM.com * @param num number of interrupt to send 949525SAndreas.Sandberg@ARM.com */ 959525SAndreas.Sandberg@ARM.com virtual void clearInt(uint32_t num) = 0; 969525SAndreas.Sandberg@ARM.com 979525SAndreas.Sandberg@ARM.com protected: 989525SAndreas.Sandberg@ARM.com /** Platform this GIC belongs to. */ 999525SAndreas.Sandberg@ARM.com Platform *platform; 1009525SAndreas.Sandberg@ARM.com}; 1019525SAndreas.Sandberg@ARM.com 10211943SCurtis.Dunham@arm.comclass BaseGicRegisters 10311943SCurtis.Dunham@arm.com{ 10411943SCurtis.Dunham@arm.com public: 10511943SCurtis.Dunham@arm.com virtual uint32_t readDistributor(ContextID ctx, Addr daddr) = 0; 10611943SCurtis.Dunham@arm.com virtual uint32_t readCpu(ContextID ctx, Addr daddr) = 0; 10711943SCurtis.Dunham@arm.com 10811943SCurtis.Dunham@arm.com virtual void writeDistributor(ContextID ctx, Addr daddr, 10911943SCurtis.Dunham@arm.com uint32_t data) = 0; 11011943SCurtis.Dunham@arm.com virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data) = 0; 11111943SCurtis.Dunham@arm.com}; 11211943SCurtis.Dunham@arm.com 11312739Sandreas.sandberg@arm.com/** 11412739Sandreas.sandberg@arm.com * Generic representation of an Arm interrupt pin. 11512739Sandreas.sandberg@arm.com */ 11612739Sandreas.sandberg@arm.comclass ArmInterruptPin : public SimObject 11712739Sandreas.sandberg@arm.com{ 11812739Sandreas.sandberg@arm.com public: 11912739Sandreas.sandberg@arm.com ArmInterruptPin(const ArmInterruptPinParams *p); 12012739Sandreas.sandberg@arm.com 12112739Sandreas.sandberg@arm.com public: /* Public interface */ 12212739Sandreas.sandberg@arm.com /** 12312739Sandreas.sandberg@arm.com * Set the thread context owning this interrupt. 12412739Sandreas.sandberg@arm.com * 12512739Sandreas.sandberg@arm.com * This method is used to set the thread context for interrupts 12612739Sandreas.sandberg@arm.com * that are thread/CPU-specific. Only devices that are used in 12712739Sandreas.sandberg@arm.com * such a context are expected to call this method. 12812739Sandreas.sandberg@arm.com */ 12912739Sandreas.sandberg@arm.com void setThreadContext(ThreadContext *tc); 13012739Sandreas.sandberg@arm.com 13112739Sandreas.sandberg@arm.com /** Signal an interrupt */ 13212739Sandreas.sandberg@arm.com virtual void raise() = 0; 13312739Sandreas.sandberg@arm.com /** Clear a signalled interrupt */ 13412739Sandreas.sandberg@arm.com virtual void clear() = 0; 13512739Sandreas.sandberg@arm.com 13612739Sandreas.sandberg@arm.com protected: 13712739Sandreas.sandberg@arm.com /** 13812739Sandreas.sandberg@arm.com * Get the target context ID of this interrupt. 13912739Sandreas.sandberg@arm.com * 14012739Sandreas.sandberg@arm.com * @pre setThreadContext() must have been called prior to calling 14112739Sandreas.sandberg@arm.com * this method. 14212739Sandreas.sandberg@arm.com */ 14312739Sandreas.sandberg@arm.com ContextID targetContext() const; 14412739Sandreas.sandberg@arm.com 14512739Sandreas.sandberg@arm.com /** 14612739Sandreas.sandberg@arm.com * Pointer to the thread context that owns this interrupt in case 14712739Sandreas.sandberg@arm.com * it is a thread-/CPU-private interrupt 14812739Sandreas.sandberg@arm.com */ 14912739Sandreas.sandberg@arm.com const ThreadContext *threadContext; 15012739Sandreas.sandberg@arm.com 15112739Sandreas.sandberg@arm.com /** Arm platform to use for interrupt generation */ 15212739Sandreas.sandberg@arm.com RealView *const platform; 15312739Sandreas.sandberg@arm.com /** Interrupt number to generate */ 15412739Sandreas.sandberg@arm.com const uint32_t intNum; 15512739Sandreas.sandberg@arm.com}; 15612739Sandreas.sandberg@arm.com 15712739Sandreas.sandberg@arm.comclass ArmSPI : public ArmInterruptPin 15812739Sandreas.sandberg@arm.com{ 15912739Sandreas.sandberg@arm.com public: 16012739Sandreas.sandberg@arm.com ArmSPI(const ArmSPIParams *p); 16112739Sandreas.sandberg@arm.com 16212739Sandreas.sandberg@arm.com void raise() override; 16312739Sandreas.sandberg@arm.com void clear() override; 16412739Sandreas.sandberg@arm.com}; 16512739Sandreas.sandberg@arm.com 16612739Sandreas.sandberg@arm.comclass ArmPPI : public ArmInterruptPin 16712739Sandreas.sandberg@arm.com{ 16812739Sandreas.sandberg@arm.com public: 16912739Sandreas.sandberg@arm.com ArmPPI(const ArmPPIParams *p); 17012739Sandreas.sandberg@arm.com 17112739Sandreas.sandberg@arm.com void raise() override; 17212739Sandreas.sandberg@arm.com void clear() override; 17312739Sandreas.sandberg@arm.com}; 17412739Sandreas.sandberg@arm.com 17512739Sandreas.sandberg@arm.com 1769525SAndreas.Sandberg@ARM.com#endif 177