a9scu.cc revision 10565:23593fdaadcd
12SN/A/* 21762SN/A * Copyright (c) 2010 ARM Limited 32SN/A * All rights reserved 42SN/A * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed hereunder. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Redistribution and use in source and binary forms, with or without 152SN/A * modification, are permitted provided that the following conditions are 162SN/A * met: redistributions of source code must retain the above copyright 172SN/A * notice, this list of conditions and the following disclaimer; 182SN/A * redistributions in binary form must reproduce the above copyright 192SN/A * notice, this list of conditions and the following disclaimer in the 202SN/A * documentation and/or other materials provided with the distribution; 212SN/A * neither the name of the copyright holders nor the names of its 222SN/A * contributors may be used to endorse or promote products derived from 232SN/A * this software without specific prior written permission. 242SN/A * 252SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282665Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 343960Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3577SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 368229Snate@binkert.org * 378229Snate@binkert.org * Authors: Ali Saidi 382986Sgblack@eecs.umich.edu */ 3956SN/A 4056SN/A#include "base/intmath.hh" 418229Snate@binkert.org#include "base/trace.hh" 422SN/A#include "dev/arm/a9scu.hh" 432SN/A#include "mem/packet.hh" 442680Sktlim@umich.edu#include "mem/packet_access.hh" 452SN/A#include "sim/system.hh" 462SN/A 471910SN/AA9SCU::A9SCU(Params *p) 483536Sgblack@eecs.umich.edu : BasicPioDevice(p, 0x60) 493536Sgblack@eecs.umich.edu{ 502SN/A} 513536Sgblack@eecs.umich.edu 523536Sgblack@eecs.umich.eduTick 533536Sgblack@eecs.umich.eduA9SCU::read(PacketPtr pkt) 543536Sgblack@eecs.umich.edu{ 553536Sgblack@eecs.umich.edu assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 563536Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 573536Sgblack@eecs.umich.edu Addr daddr = pkt->getAddr() - pioAddr; 583536Sgblack@eecs.umich.edu 593536Sgblack@eecs.umich.edu switch(daddr) { 603536Sgblack@eecs.umich.edu case Control: 613536Sgblack@eecs.umich.edu pkt->set(1); // SCU already enabled 623536Sgblack@eecs.umich.edu break; 633536Sgblack@eecs.umich.edu case Config: 643536Sgblack@eecs.umich.edu /* Without making a completely new SCU, we can use the core count field 653536Sgblack@eecs.umich.edu * as 4 bits and inform the OS of up to 16 CPUs. Although the core 663536Sgblack@eecs.umich.edu * count is technically bits [1:0] only, bits [3:2] are SBZ for future 673536Sgblack@eecs.umich.edu * expansion like this. 683536Sgblack@eecs.umich.edu */ 693536Sgblack@eecs.umich.edu if (sys->numContexts() > 4) { 703536Sgblack@eecs.umich.edu warn_once("A9SCU with >4 CPUs is unsupported\n"); 713536Sgblack@eecs.umich.edu if (sys->numContexts() > 15) 723536Sgblack@eecs.umich.edu fatal("Too many CPUs (%d) for A9SCU!\n", sys->numContexts()); 733536Sgblack@eecs.umich.edu } 743536Sgblack@eecs.umich.edu int smp_bits, core_cnt; 753536Sgblack@eecs.umich.edu smp_bits = power(2,sys->numContexts()) - 1; 763536Sgblack@eecs.umich.edu core_cnt = sys->numContexts() - 1; 773536Sgblack@eecs.umich.edu pkt->set(smp_bits << 4 | core_cnt); 783536Sgblack@eecs.umich.edu break; 793536Sgblack@eecs.umich.edu default: 803536Sgblack@eecs.umich.edu // Only configuration register is implemented 813536Sgblack@eecs.umich.edu panic("Tried to read SCU at offset %#x\n", daddr); 823536Sgblack@eecs.umich.edu break; 833536Sgblack@eecs.umich.edu } 843536Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 853536Sgblack@eecs.umich.edu return pioDelay; 863536Sgblack@eecs.umich.edu 873536Sgblack@eecs.umich.edu} 883536Sgblack@eecs.umich.edu 891910SN/ATick 901910SN/AA9SCU::write(PacketPtr pkt) 911910SN/A{ 921910SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 933536Sgblack@eecs.umich.edu 943536Sgblack@eecs.umich.edu Addr daddr = pkt->getAddr() - pioAddr; 953536Sgblack@eecs.umich.edu switch (daddr) { 963536Sgblack@eecs.umich.edu default: 973536Sgblack@eecs.umich.edu // Nothing implemented at this point 983536Sgblack@eecs.umich.edu panic("Tried to write SCU at offset %#x\n", daddr); 993536Sgblack@eecs.umich.edu break; 1003536Sgblack@eecs.umich.edu } 1013536Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 1023536Sgblack@eecs.umich.edu return pioDelay; 1033536Sgblack@eecs.umich.edu} 1043536Sgblack@eecs.umich.edu 1053536Sgblack@eecs.umich.eduA9SCU * 1062SN/AA9SCUParams::create() 1072SN/A{ 1082SN/A return new A9SCU(this); 1092SN/A} 1103536Sgblack@eecs.umich.edu