a9scu.cc revision 10186
12023SN/A/* 22023SN/A * Copyright (c) 2010 ARM Limited 32023SN/A * All rights reserved 42023SN/A * 52023SN/A * The license below extends only to copyright in the software and shall 62023SN/A * not be construed as granting a license to any other intellectual 72023SN/A * property including but not limited to intellectual property relating 82023SN/A * to a hardware implementation of the functionality of the software 92023SN/A * licensed hereunder. You may use the software subject to the license 102023SN/A * terms below provided that you ensure that this notice is replicated 112023SN/A * unmodified and in its entirety in all distributions of the software, 122023SN/A * modified or unmodified, in source code or in binary form. 132023SN/A * 142023SN/A * Redistribution and use in source and binary forms, with or without 152023SN/A * modification, are permitted provided that the following conditions are 162023SN/A * met: redistributions of source code must retain the above copyright 172023SN/A * notice, this list of conditions and the following disclaimer; 182023SN/A * redistributions in binary form must reproduce the above copyright 192023SN/A * notice, this list of conditions and the following disclaimer in the 202023SN/A * documentation and/or other materials provided with the distribution; 212023SN/A * neither the name of the copyright holders nor the names of its 222023SN/A * contributors may be used to endorse or promote products derived from 232023SN/A * this software without specific prior written permission. 242023SN/A * 252023SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262023SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282972Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 293804Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302023SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312023SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322023SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332023SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342023SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352972Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 363752Sgblack@eecs.umich.edu * 372225SN/A * Authors: Ali Saidi 383809Sgblack@eecs.umich.edu */ 392225SN/A 402225SN/A#include "base/intmath.hh" 412023SN/A#include "base/trace.hh" 422458SN/A#include "dev/arm/a9scu.hh" 432023SN/A#include "mem/packet.hh" 442458SN/A#include "mem/packet_access.hh" 452458SN/A#include "sim/system.hh" 462972Sgblack@eecs.umich.edu 472972Sgblack@eecs.umich.eduA9SCU::A9SCU(Params *p) 483809Sgblack@eecs.umich.edu : BasicPioDevice(p, 0x60) 493809Sgblack@eecs.umich.edu{ 502972Sgblack@eecs.umich.edu} 512972Sgblack@eecs.umich.edu 522972Sgblack@eecs.umich.eduTick 533437Sgblack@eecs.umich.eduA9SCU::read(PacketPtr pkt) 543093Sksewell@umich.edu{ 553093Sksewell@umich.edu assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 563414Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 573414Sgblack@eecs.umich.edu Addr daddr = pkt->getAddr() - pioAddr; 582972Sgblack@eecs.umich.edu pkt->allocate(); 592469SN/A 602469SN/A switch(daddr) { 613761Sgblack@eecs.umich.edu case Control: 623980Sgblack@eecs.umich.edu pkt->set(1); // SCU already enabled 632469SN/A break; 642469SN/A case Config: 652458SN/A /* Without making a completely new SCU, we can use the core count field 662458SN/A * as 4 bits and inform the OS of up to 16 CPUs. Although the core 672458SN/A * count is technically bits [1:0] only, bits [3:2] are SBZ for future 682458SN/A * expansion like this. 692458SN/A */ 702458SN/A if (sys->numContexts() > 4) { 712458SN/A warn_once("A9SCU with >4 CPUs is unsupported\n"); 722458SN/A if (sys->numContexts() > 15) 732458SN/A fatal("Too many CPUs (%d) for A9SCU!\n", sys->numContexts()); 742458SN/A } 752458SN/A int smp_bits, core_cnt; 762458SN/A smp_bits = power(2,sys->numContexts()) - 1; 772458SN/A core_cnt = sys->numContexts() - 1; 782510SN/A pkt->set(smp_bits << 4 | core_cnt); 792458SN/A break; 802458SN/A default: 812458SN/A // Only configuration register is implemented 822525SN/A panic("Tried to read SCU at offset %#x\n", daddr); 832561SN/A break; 842458SN/A } 852458SN/A pkt->makeAtomicResponse(); 862458SN/A return pioDelay; 872458SN/A 882458SN/A} 892458SN/A 904070Ssaidi@eecs.umich.eduTick 914070Ssaidi@eecs.umich.eduA9SCU::write(PacketPtr pkt) 924070Ssaidi@eecs.umich.edu{ 934070Ssaidi@eecs.umich.edu assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 944070Ssaidi@eecs.umich.edu 952458SN/A Addr daddr = pkt->getAddr() - pioAddr; 962458SN/A switch (daddr) { 973756Sgblack@eecs.umich.edu default: 982458SN/A // Nothing implemented at this point 992458SN/A panic("Tried to write SCU at offset %#x\n", daddr); 1002458SN/A break; 1012469SN/A } 1022458SN/A pkt->makeAtomicResponse(); 1033804Ssaidi@eecs.umich.edu return pioDelay; 1043804Ssaidi@eecs.umich.edu} 1053804Ssaidi@eecs.umich.edu 1063804Ssaidi@eecs.umich.eduA9SCU * 1073804Ssaidi@eecs.umich.eduA9SCUParams::create() 1083804Ssaidi@eecs.umich.edu{ 1093804Ssaidi@eecs.umich.edu return new A9SCU(this); 1103804Ssaidi@eecs.umich.edu} 1113804Ssaidi@eecs.umich.edu