RealView.py revision 4486
12847Sksewell@umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 27783SGiacomo.Gabrielli@arm.com# All rights reserved. 37783SGiacomo.Gabrielli@arm.com# 47783SGiacomo.Gabrielli@arm.com# Redistribution and use in source and binary forms, with or without 57783SGiacomo.Gabrielli@arm.com# modification, are permitted provided that the following conditions are 67783SGiacomo.Gabrielli@arm.com# met: redistributions of source code must retain the above copyright 77783SGiacomo.Gabrielli@arm.com# notice, this list of conditions and the following disclaimer; 87783SGiacomo.Gabrielli@arm.com# redistributions in binary form must reproduce the above copyright 97783SGiacomo.Gabrielli@arm.com# notice, this list of conditions and the following disclaimer in the 107783SGiacomo.Gabrielli@arm.com# documentation and/or other materials provided with the distribution; 117783SGiacomo.Gabrielli@arm.com# neither the name of the copyright holders nor the names of its 127783SGiacomo.Gabrielli@arm.com# contributors may be used to endorse or promote products derived from 137783SGiacomo.Gabrielli@arm.com# this software without specific prior written permission. 145596Sgblack@eecs.umich.edu# 152847Sksewell@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162847Sksewell@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172847Sksewell@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182847Sksewell@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192847Sksewell@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202847Sksewell@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212847Sksewell@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222847Sksewell@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232847Sksewell@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242847Sksewell@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252847Sksewell@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262847Sksewell@umich.edu# 272847Sksewell@umich.edu# Authors: Gabe Black 282847Sksewell@umich.edu 292847Sksewell@umich.edufrom m5.params import * 302847Sksewell@umich.edufrom m5.proxy import * 312847Sksewell@umich.edufrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr 322847Sksewell@umich.edufrom Uart import Uart8250 332847Sksewell@umich.edufrom Platform import Platform 342847Sksewell@umich.edufrom SimConsole import SimConsole 352847Sksewell@umich.edu 362847Sksewell@umich.edu 372847Sksewell@umich.educlass MmDisk(BasicPioDevice): 382847Sksewell@umich.edu type = 'MmDisk' 392847Sksewell@umich.edu image = Param.DiskImage("Disk Image") 405596Sgblack@eecs.umich.edu pio_addr = 0x1F40000000 412847Sksewell@umich.edu 422847Sksewell@umich.educlass DumbTOD(BasicPioDevice): 432847Sksewell@umich.edu type = 'DumbTOD' 442847Sksewell@umich.edu time = Param.Time('01/01/2009', "System time to use ('Now' for real time)") 452847Sksewell@umich.edu pio_addr = 0xfff0c1fff8 465596Sgblack@eecs.umich.edu 476658Snate@binkert.orgclass Iob(PioDevice): 488229Snate@binkert.org type = 'Iob' 498229Snate@binkert.org pio_latency = Param.Latency('1ns', "Programed IO latency in simticks") 505596Sgblack@eecs.umich.edu 515596Sgblack@eecs.umich.edu 522847Sksewell@umich.educlass T1000(Platform): 535596Sgblack@eecs.umich.edu type = 'T1000' 545596Sgblack@eecs.umich.edu system = Param.System(Parent.any, "system") 555596Sgblack@eecs.umich.edu 565596Sgblack@eecs.umich.edu fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000) 575596Sgblack@eecs.umich.edu #warn_access="Accessing Clock Unit -- Unimplemented!") 585596Sgblack@eecs.umich.edu 595596Sgblack@eecs.umich.edu fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384, 605596Sgblack@eecs.umich.edu ret_data64=0x0000000000000000, update_data=False) 615596Sgblack@eecs.umich.edu #warn_access="Accessing Memory Banks -- Unimplemented!") 625596Sgblack@eecs.umich.edu 635596Sgblack@eecs.umich.edu fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000) 645596Sgblack@eecs.umich.edu #warn_access="Accessing JBI -- Unimplemented!") 655596Sgblack@eecs.umich.edu 665596Sgblack@eecs.umich.edu fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8, 675596Sgblack@eecs.umich.edu ret_data64=0x0000000000000001, update_data=True) 685596Sgblack@eecs.umich.edu #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 695596Sgblack@eecs.umich.edu 705596Sgblack@eecs.umich.edu fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8, 715596Sgblack@eecs.umich.edu ret_data64=0x0000000000000001, update_data=True) 725596Sgblack@eecs.umich.edu #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 735596Sgblack@eecs.umich.edu 745596Sgblack@eecs.umich.edu fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8, 755596Sgblack@eecs.umich.edu ret_data64=0x0000000000000001, update_data=True) 765596Sgblack@eecs.umich.edu #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 775596Sgblack@eecs.umich.edu 785596Sgblack@eecs.umich.edu fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8, 795596Sgblack@eecs.umich.edu ret_data64=0x0000000000000001, update_data=True) 805596Sgblack@eecs.umich.edu #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 815596Sgblack@eecs.umich.edu 825596Sgblack@eecs.umich.edu fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8, 835596Sgblack@eecs.umich.edu ret_data64=0x0000000000000000, update_data=True) 845596Sgblack@eecs.umich.edu #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 855596Sgblack@eecs.umich.edu 865596Sgblack@eecs.umich.edu fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8, 875596Sgblack@eecs.umich.edu ret_data64=0x0000000000000000, update_data=True) 885596Sgblack@eecs.umich.edu #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 898502Sgblack@eecs.umich.edu 907720Sgblack@eecs.umich.edu fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8, 917720Sgblack@eecs.umich.edu ret_data64=0x0000000000000000, update_data=True) 925596Sgblack@eecs.umich.edu #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 935596Sgblack@eecs.umich.edu 948502Sgblack@eecs.umich.edu fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8, 955596Sgblack@eecs.umich.edu ret_data64=0x0000000000000000, update_data=True) 965596Sgblack@eecs.umich.edu #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 975596Sgblack@eecs.umich.edu 985596Sgblack@eecs.umich.edu fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000) 995596Sgblack@eecs.umich.edu #warn_access="Accessing SSI -- Unimplemented!") 1005596Sgblack@eecs.umich.edu 1015596Sgblack@eecs.umich.edu hconsole = SimConsole() 1025596Sgblack@eecs.umich.edu hvuart = Uart8250(pio_addr=0xfff0c2c000) 1035596Sgblack@eecs.umich.edu htod = DumbTOD() 1045596Sgblack@eecs.umich.edu 1055596Sgblack@eecs.umich.edu pconsole = SimConsole() 1065596Sgblack@eecs.umich.edu puart0 = Uart8250(pio_addr=0x1f10000000) 1075596Sgblack@eecs.umich.edu 1085596Sgblack@eecs.umich.edu iob = Iob() 1097783SGiacomo.Gabrielli@arm.com # Attach I/O devices that are on chip 1107783SGiacomo.Gabrielli@arm.com def attachOnChipIO(self, bus): 1117783SGiacomo.Gabrielli@arm.com self.iob.pio = bus.port 1127783SGiacomo.Gabrielli@arm.com self.htod.pio = bus.port 1137783SGiacomo.Gabrielli@arm.com 1147783SGiacomo.Gabrielli@arm.com 1157783SGiacomo.Gabrielli@arm.com # Attach I/O devices to specified bus object. Can't do this 1167783SGiacomo.Gabrielli@arm.com # earlier, since the bus object itself is typically defined at the 1177783SGiacomo.Gabrielli@arm.com # System level. 1187783SGiacomo.Gabrielli@arm.com def attachIO(self, bus): 1197783SGiacomo.Gabrielli@arm.com self.hvuart.sim_console = self.hconsole 1205596Sgblack@eecs.umich.edu self.puart0.sim_console = self.pconsole 1218471SGiacomo.Gabrielli@arm.com self.fake_clk.pio = bus.port 1228471SGiacomo.Gabrielli@arm.com self.fake_membnks.pio = bus.port 1238471SGiacomo.Gabrielli@arm.com self.fake_l2_1.pio = bus.port 1248471SGiacomo.Gabrielli@arm.com self.fake_l2_2.pio = bus.port 1258471SGiacomo.Gabrielli@arm.com self.fake_l2_3.pio = bus.port 1268471SGiacomo.Gabrielli@arm.com self.fake_l2_4.pio = bus.port 1278471SGiacomo.Gabrielli@arm.com self.fake_l2esr_1.pio = bus.port 1288471SGiacomo.Gabrielli@arm.com self.fake_l2esr_2.pio = bus.port 1298471SGiacomo.Gabrielli@arm.com self.fake_l2esr_3.pio = bus.port 1308471SGiacomo.Gabrielli@arm.com self.fake_l2esr_4.pio = bus.port 1318471SGiacomo.Gabrielli@arm.com self.fake_ssi.pio = bus.port 1325596Sgblack@eecs.umich.edu self.fake_jbi.pio = bus.port 1335596Sgblack@eecs.umich.edu self.puart0.pio = bus.port 1345596Sgblack@eecs.umich.edu self.hvuart.pio = bus.port 1355596Sgblack@eecs.umich.edu