RealView.py revision 11595
110780SCurtis.Dunham@arm.com# Copyright (c) 2009-2015 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 424486SN/A 433630SN/Afrom m5.params import * 443630SN/Afrom m5.proxy import * 4511011SAndreas.Sandberg@ARM.comfrom ClockDomain import ClockDomain 4611011SAndreas.Sandberg@ARM.comfrom VoltageDomain import VoltageDomain 477587SAli.Saidi@arm.comfrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 4811244Sandreas.sandberg@arm.comfrom PciHost import * 4910353SGeoffrey.Blake@arm.comfrom Ethernet import NSGigE, IGbE_igb, IGbE_e1000 508212SAli.Saidi@ARM.comfrom Ide import * 515478SN/Afrom Platform import Platform 525478SN/Afrom Terminal import Terminal 537584SAli.Saidi@arm.comfrom Uart import Uart 548931Sandreas.hansson@arm.comfrom SimpleMemory import SimpleMemory 559525SAndreas.Sandberg@ARM.comfrom Gic import * 5610397Sstephan.diestelhorst@arm.comfrom EnergyCtrl import EnergyCtrl 5711090Sandreas.sandberg@arm.comfrom ClockDomain import SrcClockDomain 5811236Sandreas.sandberg@arm.comfrom SubSystem import SubSystem 593630SN/A 609806Sstever@gmail.comclass AmbaPioDevice(BasicPioDevice): 619806Sstever@gmail.com type = 'AmbaPioDevice' 627584SAli.Saidi@arm.com abstract = True 639338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 647584SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 653898SN/A 669806Sstever@gmail.comclass AmbaIntDevice(AmbaPioDevice): 677950SAli.Saidi@ARM.com type = 'AmbaIntDevice' 687950SAli.Saidi@ARM.com abstract = True 699338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 709525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 717950SAli.Saidi@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 727950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 737950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 747950SAli.Saidi@ARM.com 757587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 767587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 777587SAli.Saidi@arm.com abstract = True 789338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 797753SWilliam.Wang@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 807753SWilliam.Wang@arm.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 819525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 827753SWilliam.Wang@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 837587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 847587SAli.Saidi@arm.com 858282SAli.Saidi@ARM.comclass A9SCU(BasicPioDevice): 868282SAli.Saidi@ARM.com type = 'A9SCU' 879338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/a9scu.hh" 888282SAli.Saidi@ARM.com 8911296Sandreas.sandberg@arm.comclass ArmPciIntRouting(Enum): vals = [ 9011296Sandreas.sandberg@arm.com 'ARM_PCI_INT_STATIC', 9111296Sandreas.sandberg@arm.com 'ARM_PCI_INT_DEV', 9211296Sandreas.sandberg@arm.com 'ARM_PCI_INT_PIN', 9311296Sandreas.sandberg@arm.com ] 9411296Sandreas.sandberg@arm.com 9511296Sandreas.sandberg@arm.comclass GenericArmPciHost(GenericPciHost): 9611296Sandreas.sandberg@arm.com type = 'GenericArmPciHost' 9711296Sandreas.sandberg@arm.com cxx_header = "dev/arm/pci_host.hh" 9811296Sandreas.sandberg@arm.com 9911296Sandreas.sandberg@arm.com int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy") 10011296Sandreas.sandberg@arm.com int_base = Param.Unsigned("PCI interrupt base") 10111296Sandreas.sandberg@arm.com int_count = Param.Unsigned("Maximum number of interrupts used by this host") 10211296Sandreas.sandberg@arm.com 1037584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 1047584SAli.Saidi@arm.com type = 'RealViewCtrl' 1059338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 1068524SAli.Saidi@ARM.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 1078524SAli.Saidi@ARM.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 1088299Schander.sudanthi@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 1097584SAli.Saidi@arm.com 11011011SAndreas.Sandberg@ARM.comclass RealViewOsc(ClockDomain): 11111011SAndreas.Sandberg@ARM.com type = 'RealViewOsc' 11211011SAndreas.Sandberg@ARM.com cxx_header = "dev/arm/rv_ctrl.hh" 11311011SAndreas.Sandberg@ARM.com 11411011SAndreas.Sandberg@ARM.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 11511011SAndreas.Sandberg@ARM.com 11611011SAndreas.Sandberg@ARM.com # TODO: We currently don't have the notion of a clock source, 11711011SAndreas.Sandberg@ARM.com # which means we have to associate oscillators with a voltage 11811011SAndreas.Sandberg@ARM.com # source. 11911011SAndreas.Sandberg@ARM.com voltage_domain = Param.VoltageDomain(Parent.voltage_domain, 12011011SAndreas.Sandberg@ARM.com "Voltage domain") 12111011SAndreas.Sandberg@ARM.com 12211011SAndreas.Sandberg@ARM.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 12311011SAndreas.Sandberg@ARM.com # the individual core/logic tile reference manuals for details 12411011SAndreas.Sandberg@ARM.com # about the site/position/dcc/device allocation. 12511011SAndreas.Sandberg@ARM.com site = Param.UInt8("Board Site") 12611011SAndreas.Sandberg@ARM.com position = Param.UInt8("Position in device stack") 12711011SAndreas.Sandberg@ARM.com dcc = Param.UInt8("Daughterboard Configuration Controller") 12811011SAndreas.Sandberg@ARM.com device = Param.UInt8("Device ID") 12911011SAndreas.Sandberg@ARM.com 13011011SAndreas.Sandberg@ARM.com freq = Param.Clock("Default frequency") 13111011SAndreas.Sandberg@ARM.com 13211421Sdavid.guillen@arm.comclass RealViewTemperatureSensor(SimObject): 13311421Sdavid.guillen@arm.com type = 'RealViewTemperatureSensor' 13411421Sdavid.guillen@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 13511421Sdavid.guillen@arm.com 13611421Sdavid.guillen@arm.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 13711421Sdavid.guillen@arm.com 13811421Sdavid.guillen@arm.com system = Param.System(Parent.any, "system") 13911421Sdavid.guillen@arm.com 14011421Sdavid.guillen@arm.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 14111421Sdavid.guillen@arm.com # the individual core/logic tile reference manuals for details 14211421Sdavid.guillen@arm.com # about the site/position/dcc/device allocation. 14311421Sdavid.guillen@arm.com site = Param.UInt8("Board Site") 14411421Sdavid.guillen@arm.com position = Param.UInt8("Position in device stack") 14511421Sdavid.guillen@arm.com dcc = Param.UInt8("Daughterboard Configuration Controller") 14611421Sdavid.guillen@arm.com device = Param.UInt8("Device ID") 14711421Sdavid.guillen@arm.com 14811236Sandreas.sandberg@arm.comclass VExpressMCC(SubSystem): 14911236Sandreas.sandberg@arm.com """ARM V2M-P1 Motherboard Configuration Controller 15011236Sandreas.sandberg@arm.com 15111236Sandreas.sandberg@arm.comThis subsystem describes a subset of the devices that sit behind the 15211236Sandreas.sandberg@arm.commotherboard configuration controller on the the ARM Motherboard 15311236Sandreas.sandberg@arm.comExpress (V2M-P1) motherboard. See ARM DUI 0447J for details. 15411236Sandreas.sandberg@arm.com """ 15511236Sandreas.sandberg@arm.com 15611236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 15711011SAndreas.Sandberg@ARM.com site, position, dcc = (0, 0, 0) 15811011SAndreas.Sandberg@ARM.com 15911421Sdavid.guillen@arm.com class Temperature(RealViewTemperatureSensor): 16011421Sdavid.guillen@arm.com site, position, dcc = (0, 0, 0) 16111421Sdavid.guillen@arm.com 16211236Sandreas.sandberg@arm.com osc_mcc = Osc(device=0, freq="50MHz") 16311236Sandreas.sandberg@arm.com osc_clcd = Osc(device=1, freq="23.75MHz") 16411236Sandreas.sandberg@arm.com osc_peripheral = Osc(device=2, freq="24MHz") 16511236Sandreas.sandberg@arm.com osc_system_bus = Osc(device=4, freq="24MHz") 16611236Sandreas.sandberg@arm.com 16711421Sdavid.guillen@arm.com # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM). 16811421Sdavid.guillen@arm.com temp_crtl = Temperature(device=0) 16911421Sdavid.guillen@arm.com 17011236Sandreas.sandberg@arm.comclass CoreTile2A15DCC(SubSystem): 17111236Sandreas.sandberg@arm.com """ARM CoreTile Express A15x2 Daughterboard Configuration Controller 17211236Sandreas.sandberg@arm.com 17311236Sandreas.sandberg@arm.comThis subsystem describes a subset of the devices that sit behind the 17411236Sandreas.sandberg@arm.comdaughterboard configuration controller on a CoreTile Express A15x2. See 17511236Sandreas.sandberg@arm.comARM DUI 0604E for details. 17611236Sandreas.sandberg@arm.com """ 17711236Sandreas.sandberg@arm.com 17811236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 17911011SAndreas.Sandberg@ARM.com site, position, dcc = (1, 0, 0) 18011011SAndreas.Sandberg@ARM.com 18111236Sandreas.sandberg@arm.com # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM) 18211236Sandreas.sandberg@arm.com osc_cpu = Osc(device=0, freq="60MHz") 18311236Sandreas.sandberg@arm.com osc_hsbm = Osc(device=4, freq="40MHz") 18411236Sandreas.sandberg@arm.com osc_pxl = Osc(device=5, freq="23.75MHz") 18511236Sandreas.sandberg@arm.com osc_smb = Osc(device=6, freq="50MHz") 18611236Sandreas.sandberg@arm.com osc_sys = Osc(device=7, freq="60MHz") 18711236Sandreas.sandberg@arm.com osc_ddr = Osc(device=8, freq="40MHz") 18811011SAndreas.Sandberg@ARM.com 18910037SARM gem5 Developersclass VGic(PioDevice): 19010037SARM gem5 Developers type = 'VGic' 19110037SARM gem5 Developers cxx_header = "dev/arm/vgic.hh" 19210037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 19310037SARM gem5 Developers platform = Param.Platform(Parent.any, "Platform this device is part of.") 19410037SARM gem5 Developers vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 19510037SARM gem5 Developers hv_addr = Param.Addr(0, "Address for hv control") 19610037SARM gem5 Developers pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 19710037SARM gem5 Developers # The number of list registers is not currently configurable at runtime. 19810037SARM gem5 Developers ppint = Param.UInt32("HV maintenance interrupt number") 19910037SARM gem5 Developers 2009806Sstever@gmail.comclass AmbaFake(AmbaPioDevice): 2017584SAli.Saidi@arm.com type = 'AmbaFake' 2029338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_fake.hh" 2037584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 2047584SAli.Saidi@arm.com amba_id = 0; 2057584SAli.Saidi@arm.com 2067584SAli.Saidi@arm.comclass Pl011(Uart): 2077584SAli.Saidi@arm.com type = 'Pl011' 2089338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl011.hh" 2099525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 2107584SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 2117584SAli.Saidi@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 2127584SAli.Saidi@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 2137584SAli.Saidi@arm.com 2149806Sstever@gmail.comclass Sp804(AmbaPioDevice): 2157584SAli.Saidi@arm.com type = 'Sp804' 2169338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_sp804.hh" 2179525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 2187584SAli.Saidi@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 2197584SAli.Saidi@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 2207584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 2217584SAli.Saidi@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 2227584SAli.Saidi@arm.com amba_id = 0x00141804 2237584SAli.Saidi@arm.com 2248512Sgeoffrey.blake@arm.comclass CpuLocalTimer(BasicPioDevice): 2258512Sgeoffrey.blake@arm.com type = 'CpuLocalTimer' 2269338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_cpulocal.hh" 2279525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 2288512Sgeoffrey.blake@arm.com int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 2298512Sgeoffrey.blake@arm.com int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 2308512Sgeoffrey.blake@arm.com 23110037SARM gem5 Developersclass GenericTimer(SimObject): 23210037SARM gem5 Developers type = 'GenericTimer' 23310037SARM gem5 Developers cxx_header = "dev/arm/generic_timer.hh" 23410037SARM gem5 Developers system = Param.System(Parent.any, "system") 23510037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 23610845Sandreas.sandberg@arm.com # @todo: for now only two timers per CPU is supported, which is the 23710845Sandreas.sandberg@arm.com # normal behaviour when security extensions are disabled. 23810845Sandreas.sandberg@arm.com int_phys = Param.UInt32("Physical timer interrupt number") 23910845Sandreas.sandberg@arm.com int_virt = Param.UInt32("Virtual timer interrupt number") 24010037SARM gem5 Developers 24110847Sandreas.sandberg@arm.comclass GenericTimerMem(PioDevice): 24210847Sandreas.sandberg@arm.com type = 'GenericTimerMem' 24310847Sandreas.sandberg@arm.com cxx_header = "dev/arm/generic_timer.hh" 24410847Sandreas.sandberg@arm.com gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 24510847Sandreas.sandberg@arm.com 24610847Sandreas.sandberg@arm.com base = Param.Addr(0, "Base address") 24710847Sandreas.sandberg@arm.com 24810847Sandreas.sandberg@arm.com int_phys = Param.UInt32("Interrupt number") 24910847Sandreas.sandberg@arm.com int_virt = Param.UInt32("Interrupt number") 25010847Sandreas.sandberg@arm.com 2518870SAli.Saidi@ARM.comclass PL031(AmbaIntDevice): 2528870SAli.Saidi@ARM.com type = 'PL031' 2539338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rtc_pl031.hh" 2548870SAli.Saidi@ARM.com time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 2558870SAli.Saidi@ARM.com amba_id = 0x00341031 2568870SAli.Saidi@ARM.com 2577950SAli.Saidi@ARM.comclass Pl050(AmbaIntDevice): 2587754SWilliam.Wang@arm.com type = 'Pl050' 2599338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/kmi.hh" 2609330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 2617950SAli.Saidi@ARM.com is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 2627950SAli.Saidi@ARM.com int_delay = '1us' 2637754SWilliam.Wang@arm.com amba_id = 0x00141050 2647754SWilliam.Wang@arm.com 2657753SWilliam.Wang@arm.comclass Pl111(AmbaDmaDevice): 2667753SWilliam.Wang@arm.com type = 'Pl111' 2679338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl111.hh" 2689394Sandreas.hansson@arm.com pixel_clock = Param.Clock('24MHz', "Pixel clock") 2699330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 2707753SWilliam.Wang@arm.com amba_id = 0x00141111 2719939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 2729939Sdam.sunwoo@arm.com 2739646SChris.Emmons@arm.comclass HDLcd(AmbaDmaDevice): 2749646SChris.Emmons@arm.com type = 'HDLcd' 2759646SChris.Emmons@arm.com cxx_header = "dev/arm/hdlcd.hh" 2769646SChris.Emmons@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 2779646SChris.Emmons@arm.com "display") 2789646SChris.Emmons@arm.com amba_id = 0x00141000 27911237Sandreas.sandberg@arm.com workaround_swap_rb = Param.Bool(False, "Workaround incorrect color " 28010840Sandreas.sandberg@arm.com "selector order in some kernels") 28111090Sandreas.sandberg@arm.com workaround_dma_line_count = Param.Bool(True, "Workaround incorrect " 28211090Sandreas.sandberg@arm.com "DMA line count (off by 1)") 2839939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 2849646SChris.Emmons@arm.com 28511090Sandreas.sandberg@arm.com pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range") 28611090Sandreas.sandberg@arm.com 28711090Sandreas.sandberg@arm.com pxl_clk = Param.ClockDomain("Pixel clock source") 28811090Sandreas.sandberg@arm.com pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 28911090Sandreas.sandberg@arm.com 2907584SAli.Saidi@arm.comclass RealView(Platform): 2917584SAli.Saidi@arm.com type = 'RealView' 2929338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/realview.hh" 2933630SN/A system = Param.System(Parent.any, "system") 29410358SAli.Saidi@ARM.com _mem_regions = [(Addr(0), Addr('256MB'))] 2958870SAli.Saidi@ARM.com 29611297Sandreas.sandberg@arm.com def _on_chip_devices(self): 29711297Sandreas.sandberg@arm.com return [] 29811297Sandreas.sandberg@arm.com 29911297Sandreas.sandberg@arm.com def _off_chip_devices(self): 30011297Sandreas.sandberg@arm.com return [] 30111297Sandreas.sandberg@arm.com 30211297Sandreas.sandberg@arm.com _off_chip_ranges = [] 30311297Sandreas.sandberg@arm.com 30411297Sandreas.sandberg@arm.com def _attach_io(self, devices, bus): 30511297Sandreas.sandberg@arm.com for d in devices: 30611297Sandreas.sandberg@arm.com if hasattr(d, "pio"): 30711297Sandreas.sandberg@arm.com d.pio = bus.master 30811297Sandreas.sandberg@arm.com if hasattr(d, "dma"): 30911297Sandreas.sandberg@arm.com d.dma = bus.slave 31011297Sandreas.sandberg@arm.com 31111297Sandreas.sandberg@arm.com def _attach_clk(self, devices, clkdomain): 31211297Sandreas.sandberg@arm.com for d in devices: 31311297Sandreas.sandberg@arm.com if hasattr(d, "clk_domain"): 31411297Sandreas.sandberg@arm.com d.clk_domain = clkdomain 31511297Sandreas.sandberg@arm.com 31610353SGeoffrey.Blake@arm.com def attachPciDevices(self): 31710353SGeoffrey.Blake@arm.com pass 31810353SGeoffrey.Blake@arm.com 31910353SGeoffrey.Blake@arm.com def enableMSIX(self): 32010353SGeoffrey.Blake@arm.com pass 32110353SGeoffrey.Blake@arm.com 32210353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 32311297Sandreas.sandberg@arm.com self._attach_clk(self._on_chip_devices(), clkdomain) 32410353SGeoffrey.Blake@arm.com 32510353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 32611297Sandreas.sandberg@arm.com self._attach_clk(self._off_chip_devices(), clkdomain) 32711297Sandreas.sandberg@arm.com 32811297Sandreas.sandberg@arm.com def attachOnChipIO(self, bus, bridge=None): 32911297Sandreas.sandberg@arm.com self._attach_io(self._on_chip_devices(), bus) 33011297Sandreas.sandberg@arm.com if bridge: 33111297Sandreas.sandberg@arm.com bridge.ranges = self._off_chip_ranges 33211297Sandreas.sandberg@arm.com 33311297Sandreas.sandberg@arm.com def attachIO(self, bus): 33411297Sandreas.sandberg@arm.com self._attach_io(self._off_chip_devices(), bus) 33511297Sandreas.sandberg@arm.com 33610353SGeoffrey.Blake@arm.com 3378870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 3389835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 3399835Sandreas.hansson@arm.com conf_table_reported = False) 3408870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 3418870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot.arm') 34210037SARM gem5 Developers cur_sys.atags_addr = 0x100 34310037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 34410037SARM gem5 Developers cur_sys.load_offset = 0 3458870SAli.Saidi@ARM.com 3463630SN/A 3477753SWilliam.Wang@arm.com# Reference for memory map and interrupt number 3487753SWilliam.Wang@arm.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 3497753SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 3507584SAli.Saidi@arm.comclass RealViewPBX(RealView): 3517584SAli.Saidi@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 35211236Sandreas.sandberg@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000) 35311236Sandreas.sandberg@arm.com mcc = VExpressMCC() 35411236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 3559525SAndreas.Sandberg@ARM.com gic = Pl390() 35611244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 35711244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 35811244Sandreas.sandberg@arm.com pci_pio_base=0) 3597584SAli.Saidi@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 3607584SAli.Saidi@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 3618512Sgeoffrey.blake@arm.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 3627753SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=55) 3637754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 3647950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 3658282SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0x1f000000) 3668525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 3678212SAli.Saidi@ARM.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 3688212SAli.Saidi@ARM.com BAR0 = 0x18000000, BAR0Size = '16B', 3698212SAli.Saidi@ARM.com BAR1 = 0x18000100, BAR1Size = '1B', 3708212SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 3718212SAli.Saidi@ARM.com 3727584SAli.Saidi@arm.com 3737731SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 3748461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 3758461SAli.Saidi@ARM.com fake_mem=True) 3767696SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0x10030000) 3777696SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 3787696SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 3797696SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 3807696SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 3817696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 3827696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 3837696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 3847696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 3857696SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 3867696SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 3877696SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 3887696SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 3897696SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 3908906Skoansin.tan@gmail.com rtc = PL031(pio_addr=0x10017000, int_num=42) 39110397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 3927696SAli.Saidi@ARM.com 3937696SAli.Saidi@ARM.com 3948713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 3958713Sandreas.hansson@arm.com # ranges for the bridge 3968713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 3978839Sandreas.hansson@arm.com self.gic.pio = bus.master 3988839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 3998839Sandreas.hansson@arm.com self.a9scu.pio = bus.master 4008839Sandreas.hansson@arm.com self.local_cpu_timer.pio = bus.master 4018713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 4028713Sandreas.hansson@arm.com # (gic, l2x0, a9scu, local_cpu_timer) 4038713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 4048713Sandreas.hansson@arm.com self.a9scu.pio_addr - 1), 4058870SAli.Saidi@ARM.com AddrRange(self.flash_fake.pio_addr, 4068870SAli.Saidi@ARM.com self.flash_fake.pio_addr + \ 4078870SAli.Saidi@ARM.com self.flash_fake.pio_size - 1)] 4087696SAli.Saidi@ARM.com 40910353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 41010353SGeoffrey.Blake@arm.com # to be "close" to the cores. 41110353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 41210353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 41310353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 41410353SGeoffrey.Blake@arm.com self.a9scu.clkdomain = clkdomain 41510353SGeoffrey.Blake@arm.com self.local_cpu_timer.clk_domain = clkdomain 41610353SGeoffrey.Blake@arm.com 4177696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 4187696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 4197696SAli.Saidi@ARM.com # System level. 4207696SAli.Saidi@ARM.com def attachIO(self, bus): 4218839Sandreas.hansson@arm.com self.uart.pio = bus.master 4228839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 42311244Sandreas.sandberg@arm.com self.pci_host.pio = bus.master 4248839Sandreas.hansson@arm.com self.timer0.pio = bus.master 4258839Sandreas.hansson@arm.com self.timer1.pio = bus.master 4268839Sandreas.hansson@arm.com self.clcd.pio = bus.master 4278839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 4288839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 4298839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 4308839Sandreas.hansson@arm.com self.cf_ctrl.pio = bus.master 4318839Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.slave 4328839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 4338839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 4348839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 4358839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 4368839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 4378839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 4388839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 4398839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 4408839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 4418839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 4428839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 4438839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 4448839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 4458839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 4468906Skoansin.tan@gmail.com self.rtc.pio = bus.master 4478839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 44810397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 4497696SAli.Saidi@ARM.com 45010353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 45110353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 45210353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 45310353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 45410353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 45510353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 45610353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 45710353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 45810353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 45910353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 46010353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 46110353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 46210353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 46310353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 46410353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 46510353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 46610353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 46710353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 46810353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 46910353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 47010353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 47110353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 47210353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 47310353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 47410353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 47510353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 47610353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 47710397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 47810353SGeoffrey.Blake@arm.com 4797754SWilliam.Wang@arm.com# Reference for memory map and interrupt number 4807754SWilliam.Wang@arm.com# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 4817754SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 4827696SAli.Saidi@ARM.comclass RealViewEB(RealView): 4837696SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x10009000, int_num=44) 48411236Sandreas.sandberg@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) 48511236Sandreas.sandberg@arm.com mcc = VExpressMCC() 48611236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 4879525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 4887696SAli.Saidi@ARM.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 4897696SAli.Saidi@ARM.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 4907754SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=23) 4917754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 4927950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 4937696SAli.Saidi@ARM.com 4947696SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 4958461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 4968461SAli.Saidi@ARM.com fake_mem=True) 4977584SAli.Saidi@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 4987584SAli.Saidi@arm.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 4997584SAli.Saidi@arm.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 5007584SAli.Saidi@arm.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 5018299Schander.sudanthi@arm.com smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 5027584SAli.Saidi@arm.com smc_fake = AmbaFake(pio_addr=0x100e1000) 5037584SAli.Saidi@arm.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 5047584SAli.Saidi@arm.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 5057584SAli.Saidi@arm.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 5067584SAli.Saidi@arm.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 5077584SAli.Saidi@arm.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 5087584SAli.Saidi@arm.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 5097584SAli.Saidi@arm.com sci_fake = AmbaFake(pio_addr=0x1000e000) 5107584SAli.Saidi@arm.com aaci_fake = AmbaFake(pio_addr=0x10004000) 5117584SAli.Saidi@arm.com mmc_fake = AmbaFake(pio_addr=0x10005000) 5127584SAli.Saidi@arm.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 51310397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 5147584SAli.Saidi@arm.com 5158713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 5168713Sandreas.hansson@arm.com # ranges for the bridge 5178713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 5188839Sandreas.hansson@arm.com self.gic.pio = bus.master 5198839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 5208713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 5218713Sandreas.hansson@arm.com # (gic, l2x0) 5228713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 5238713Sandreas.hansson@arm.com self.gic.cpu_addr - 1), 5248713Sandreas.hansson@arm.com AddrRange(self.flash_fake.pio_addr, Addr.max)] 5254104SN/A 52610353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 52710353SGeoffrey.Blake@arm.com # to be "close" to the cores. 52810353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 52910353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 53010353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 53110353SGeoffrey.Blake@arm.com 5323630SN/A # Attach I/O devices to specified bus object. Can't do this 5333630SN/A # earlier, since the bus object itself is typically defined at the 5343630SN/A # System level. 5353630SN/A def attachIO(self, bus): 5368839Sandreas.hansson@arm.com self.uart.pio = bus.master 5378839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 53811244Sandreas.sandberg@arm.com self.pci_host.pio = bus.master 5398839Sandreas.hansson@arm.com self.timer0.pio = bus.master 5408839Sandreas.hansson@arm.com self.timer1.pio = bus.master 5418839Sandreas.hansson@arm.com self.clcd.pio = bus.master 5428839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 5438839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 5448839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 5458839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 5468839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 5478839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 5488839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 5498839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 5508839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 5518839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 5528839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 5538839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 5548839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 5558839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 5568839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 5578839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 5588839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 5598839Sandreas.hansson@arm.com self.rtc_fake.pio = bus.master 5608839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 5618839Sandreas.hansson@arm.com self.smcreg_fake.pio = bus.master 56210397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 5637584SAli.Saidi@arm.com 56410353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 56510353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 56610353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 56710353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 56810353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 56910353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 57010353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 57110353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 57210353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 57310353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 57410353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 57510353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 57610353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 57710353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 57810353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 57910353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 58010353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 58110353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 58210353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 58310353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 58410353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 58510353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 58610353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 58710353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 58810353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 58910353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 59010353SGeoffrey.Blake@arm.com self.smcreg_fake.clk_domain = clkdomain 59110397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 59210353SGeoffrey.Blake@arm.com 5938870SAli.Saidi@ARM.comclass VExpress_EMM(RealView): 59410358SAli.Saidi@ARM.com _mem_regions = [(Addr('2GB'), Addr('2GB'))] 5958870SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x1c090000, int_num=37) 59611236Sandreas.sandberg@arm.com realview_io = RealViewCtrl( 59711011SAndreas.Sandberg@ARM.com proc_id0=0x14000000, proc_id1=0x14000000, 59811011SAndreas.Sandberg@ARM.com idreg=0x02250000, pio_addr=0x1C010000) 59911236Sandreas.sandberg@arm.com mcc = VExpressMCC() 60011236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 6019525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 60211244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 60311244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 60411244Sandreas.sandberg@arm.com pci_pio_base=0) 6058870SAli.Saidi@ARM.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 60610845Sandreas.sandberg@arm.com generic_timer = GenericTimer(int_phys=29, int_virt=27) 6079185SAli.Saidi@ARM.com timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 6089185SAli.Saidi@ARM.com timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 6098870SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 61011236Sandreas.sandberg@arm.com hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 61111237Sandreas.sandberg@arm.com pio_addr=0x2b000000, int_num=117, 61211237Sandreas.sandberg@arm.com workaround_swap_rb=True) 6138870SAli.Saidi@ARM.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 6149387SChris.Emmons@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 61510037SARM gem5 Developers vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 6168870SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 6178870SAli.Saidi@ARM.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 6188870SAli.Saidi@ARM.com BAR0 = 0x1C1A0000, BAR0Size = '256B', 6198870SAli.Saidi@ARM.com BAR1 = 0x1C1A0100, BAR1Size = '4096B', 6208870SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 6219052Sgeoffrey.blake@arm.com 6229835Sandreas.hansson@arm.com vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 6239835Sandreas.hansson@arm.com conf_table_reported = False) 6248870SAli.Saidi@ARM.com rtc = PL031(pio_addr=0x1C170000, int_num=36) 6258870SAli.Saidi@ARM.com 6268870SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 6278870SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 6288870SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 6298870SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 6308870SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 6318870SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 6328870SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x1C040000) 6338870SAli.Saidi@ARM.com lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 6348870SAli.Saidi@ARM.com usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 6358870SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x1c050000) 63610397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 6378870SAli.Saidi@ARM.com 63810353SGeoffrey.Blake@arm.com # Attach any PCI devices that are supported 63910353SGeoffrey.Blake@arm.com def attachPciDevices(self): 64010353SGeoffrey.Blake@arm.com self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 64110353SGeoffrey.Blake@arm.com InterruptLine=1, InterruptPin=1) 64210353SGeoffrey.Blake@arm.com self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 64310353SGeoffrey.Blake@arm.com InterruptLine=2, InterruptPin=2) 64410353SGeoffrey.Blake@arm.com 64510353SGeoffrey.Blake@arm.com def enableMSIX(self): 64610353SGeoffrey.Blake@arm.com self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 64710353SGeoffrey.Blake@arm.com self.gicv2m = Gicv2m() 64810353SGeoffrey.Blake@arm.com self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 64910353SGeoffrey.Blake@arm.com 6508870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 6519835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('64MB'), 6529835Sandreas.hansson@arm.com conf_table_reported = False) 6538870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 6548870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot_emm.arm') 65510037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 65610037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 65710037SARM gem5 Developers cur_sys.load_offset = 0x80000000 6588870SAli.Saidi@ARM.com 6598870SAli.Saidi@ARM.com # Attach I/O devices that are on chip and also set the appropriate 6608870SAli.Saidi@ARM.com # ranges for the bridge 66110780SCurtis.Dunham@arm.com def attachOnChipIO(self, bus, bridge=None): 66210780SCurtis.Dunham@arm.com self.gic.pio = bus.master 66310780SCurtis.Dunham@arm.com self.vgic.pio = bus.master 66410780SCurtis.Dunham@arm.com self.local_cpu_timer.pio = bus.master 66510780SCurtis.Dunham@arm.com if hasattr(self, "gicv2m"): 66610780SCurtis.Dunham@arm.com self.gicv2m.pio = bus.master 66710780SCurtis.Dunham@arm.com self.hdlcd.dma = bus.slave 66810780SCurtis.Dunham@arm.com if bridge: 66910780SCurtis.Dunham@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 67010780SCurtis.Dunham@arm.com # (gic, a9scu) 67110780SCurtis.Dunham@arm.com bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 67210780SCurtis.Dunham@arm.com AddrRange(0x2B000000, size='4MB'), 67310780SCurtis.Dunham@arm.com AddrRange(0x30000000, size='256MB'), 67410780SCurtis.Dunham@arm.com AddrRange(0x40000000, size='512MB'), 67510780SCurtis.Dunham@arm.com AddrRange(0x18000000, size='64MB'), 67610780SCurtis.Dunham@arm.com AddrRange(0x1C000000, size='64MB')] 67710037SARM gem5 Developers 6788870SAli.Saidi@ARM.com 67910353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 68010353SGeoffrey.Blake@arm.com # to be "close" to the cores. 68110353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 68210353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 68310353SGeoffrey.Blake@arm.com if hasattr(self, "gicv2m"): 68410353SGeoffrey.Blake@arm.com self.gicv2m.clk_domain = clkdomain 68510353SGeoffrey.Blake@arm.com self.hdlcd.clk_domain = clkdomain 68610353SGeoffrey.Blake@arm.com self.vgic.clk_domain = clkdomain 68710353SGeoffrey.Blake@arm.com 68810353SGeoffrey.Blake@arm.com # Attach I/O devices to specified bus object. Done here 68910353SGeoffrey.Blake@arm.com # as the specified bus to connect to may not always be fixed. 6908870SAli.Saidi@ARM.com def attachIO(self, bus): 6918870SAli.Saidi@ARM.com self.uart.pio = bus.master 6928870SAli.Saidi@ARM.com self.realview_io.pio = bus.master 69311244Sandreas.sandberg@arm.com self.pci_host.pio = bus.master 6948870SAli.Saidi@ARM.com self.timer0.pio = bus.master 6958870SAli.Saidi@ARM.com self.timer1.pio = bus.master 6968870SAli.Saidi@ARM.com self.clcd.pio = bus.master 6978870SAli.Saidi@ARM.com self.clcd.dma = bus.slave 6989646SChris.Emmons@arm.com self.hdlcd.pio = bus.master 6998870SAli.Saidi@ARM.com self.kmi0.pio = bus.master 7008870SAli.Saidi@ARM.com self.kmi1.pio = bus.master 7018870SAli.Saidi@ARM.com self.cf_ctrl.pio = bus.master 7028872Ssaidi@eecs.umich.edu self.cf_ctrl.dma = bus.slave 7038870SAli.Saidi@ARM.com self.rtc.pio = bus.master 7048870SAli.Saidi@ARM.com self.vram.port = bus.master 7058870SAli.Saidi@ARM.com 7068870SAli.Saidi@ARM.com self.l2x0_fake.pio = bus.master 7078870SAli.Saidi@ARM.com self.uart1_fake.pio = bus.master 7088870SAli.Saidi@ARM.com self.uart2_fake.pio = bus.master 7098870SAli.Saidi@ARM.com self.uart3_fake.pio = bus.master 7108870SAli.Saidi@ARM.com self.sp810_fake.pio = bus.master 7118870SAli.Saidi@ARM.com self.watchdog_fake.pio = bus.master 7128870SAli.Saidi@ARM.com self.aaci_fake.pio = bus.master 7138870SAli.Saidi@ARM.com self.lan_fake.pio = bus.master 7148870SAli.Saidi@ARM.com self.usb_fake.pio = bus.master 7158870SAli.Saidi@ARM.com self.mmc_fake.pio = bus.master 71610397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 7178870SAli.Saidi@ARM.com 71810353SGeoffrey.Blake@arm.com # Try to attach the I/O if it exists 71910353SGeoffrey.Blake@arm.com try: 72010353SGeoffrey.Blake@arm.com self.ide.pio = bus.master 72110353SGeoffrey.Blake@arm.com self.ide.dma = bus.slave 72210353SGeoffrey.Blake@arm.com self.ethernet.pio = bus.master 72310353SGeoffrey.Blake@arm.com self.ethernet.dma = bus.slave 72410353SGeoffrey.Blake@arm.com except: 72510353SGeoffrey.Blake@arm.com pass 72610353SGeoffrey.Blake@arm.com 72710353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 72810353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 72910353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 73010353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 73110353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 73210353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 73310353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 73410353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 73510353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 73610353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 73710353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 73810353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 73910353SGeoffrey.Blake@arm.com self.vram.clk_domain = clkdomain 74010353SGeoffrey.Blake@arm.com 74110353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 74210353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 74310353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 74410353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 74510353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 74610353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 74710353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 74810353SGeoffrey.Blake@arm.com self.lan_fake.clk_domain = clkdomain 74910353SGeoffrey.Blake@arm.com self.usb_fake.clk_domain = clkdomain 75010353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 75110397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 75210353SGeoffrey.Blake@arm.com 75310037SARM gem5 Developersclass VExpress_EMM64(VExpress_EMM): 75410358SAli.Saidi@ARM.com # Three memory regions are specified totalling 512GB 75510358SAli.Saidi@ARM.com _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 75610358SAli.Saidi@ARM.com (Addr('512GB'), Addr('480GB'))] 75711244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 75811244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 75911244Sandreas.sandberg@arm.com pci_pio_base=0x2f000000) 76011244Sandreas.sandberg@arm.com 76110037SARM gem5 Developers def setupBootLoader(self, mem_bus, cur_sys, loc): 76211595Sandreas.sandberg@arm.com self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'), 76311595Sandreas.sandberg@arm.com conf_table_reported=False) 76410037SARM gem5 Developers self.nvmem.port = mem_bus.master 76510037SARM gem5 Developers cur_sys.boot_loader = loc('boot_emm.arm64') 76610037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 76710037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 76810037SARM gem5 Developers cur_sys.load_offset = 0x80000000 76910037SARM gem5 Developers 77010037SARM gem5 Developers 77111297Sandreas.sandberg@arm.comclass VExpress_GEM5_V1(RealView): 77211297Sandreas.sandberg@arm.com """ 77311297Sandreas.sandberg@arm.comThe VExpress gem5 memory map is loosely based on a modified 77411297Sandreas.sandberg@arm.comVersatile Express RS1 memory map. 77511297Sandreas.sandberg@arm.com 77611297Sandreas.sandberg@arm.comThe gem5 platform has been designed to implement a subset of the 77711297Sandreas.sandberg@arm.comoriginal Versatile Express RS1 memory map. Off-chip peripherals should, 77811297Sandreas.sandberg@arm.comwhen possible, adhere to the Versatile Express memory map. Non-PCI 77911297Sandreas.sandberg@arm.comoff-chip devices that are gem5-specific should live in the CS5 memory 78011297Sandreas.sandberg@arm.comspace to avoid conflicts with existing devices that we might want to 78111297Sandreas.sandberg@arm.commodel in the future. Such devices should normally have interrupts in 78211297Sandreas.sandberg@arm.comthe gem5-specific SPI range. 78311297Sandreas.sandberg@arm.com 78411297Sandreas.sandberg@arm.comOn-chip peripherals are loosely modeled after the ARM CoreTile Express 78511297Sandreas.sandberg@arm.comA15x2 A7x3 memory and interrupt map. In particular, the GIC and 78611297Sandreas.sandberg@arm.comGeneric Timer have the same interrupt lines and base addresses. Other 78711297Sandreas.sandberg@arm.comon-chip devices are gem5 specific. 78811297Sandreas.sandberg@arm.com 78911297Sandreas.sandberg@arm.comUnlike the original Versatile Express RS2 extended platform, gem5 implements a 79011297Sandreas.sandberg@arm.comlarge contigious DRAM space, without aliases or holes, starting at the 79111297Sandreas.sandberg@arm.com2GiB boundary. This means that PCI memory is limited to 1GiB. 79211297Sandreas.sandberg@arm.com 79311297Sandreas.sandberg@arm.comMemory map: 79411297Sandreas.sandberg@arm.com 0x00000000-0x03ffffff: Boot memory (CS0) 79511297Sandreas.sandberg@arm.com 0x04000000-0x07ffffff: Reserved 79611297Sandreas.sandberg@arm.com 0x08000000-0x0bffffff: Reserved (CS0 alias) 79711297Sandreas.sandberg@arm.com 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4) 79811297Sandreas.sandberg@arm.com 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5) 79911297Sandreas.sandberg@arm.com 0x10000000-0x1000ffff: gem5 energy controller 80011297Sandreas.sandberg@arm.com 80111297Sandreas.sandberg@arm.com 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1) 80211297Sandreas.sandberg@arm.com 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2) 80311297Sandreas.sandberg@arm.com 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3): 80411297Sandreas.sandberg@arm.com 0x1c010000-0x1c01ffff: realview_io (VE system control regs.) 80511297Sandreas.sandberg@arm.com 0x1c060000-0x1c06ffff: KMI0 (keyboard) 80611297Sandreas.sandberg@arm.com 0x1c070000-0x1c07ffff: KMI1 (mouse) 80711297Sandreas.sandberg@arm.com 0x1c090000-0x1c09ffff: UART0 80811297Sandreas.sandberg@arm.com 0x1c0a0000-0x1c0affff: UART1 (reserved) 80911297Sandreas.sandberg@arm.com 0x1c0b0000-0x1c0bffff: UART2 (reserved) 81011297Sandreas.sandberg@arm.com 0x1c0c0000-0x1c0cffff: UART3 (reserved) 81111297Sandreas.sandberg@arm.com 0x1c170000-0x1c17ffff: RTC 81211297Sandreas.sandberg@arm.com 81311297Sandreas.sandberg@arm.com 0x20000000-0x3fffffff: On-chip peripherals: 81411297Sandreas.sandberg@arm.com 0x2b000000-0x2b00ffff: HDLCD 81511297Sandreas.sandberg@arm.com 81611297Sandreas.sandberg@arm.com 0x2c001000-0x2c001fff: GIC (distributor) 81711297Sandreas.sandberg@arm.com 0x2c002000-0x2c0020ff: GIC (CPU interface) 81811297Sandreas.sandberg@arm.com 0x2c004000-0x2c005fff: vGIC (HV) 81911297Sandreas.sandberg@arm.com 0x2c006000-0x2c007fff: vGIC (VCPU) 82011297Sandreas.sandberg@arm.com 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0 82111297Sandreas.sandberg@arm.com 82211297Sandreas.sandberg@arm.com 0x2d000000-0x2d00ffff: GPU (reserved) 82311297Sandreas.sandberg@arm.com 82411297Sandreas.sandberg@arm.com 0x2f000000-0x2fffffff: PCI IO space 82511297Sandreas.sandberg@arm.com 0x30000000-0x3fffffff: PCI config space 82611297Sandreas.sandberg@arm.com 82711297Sandreas.sandberg@arm.com 0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory 82811297Sandreas.sandberg@arm.com 82911297Sandreas.sandberg@arm.com 0x80000000-X: DRAM 83011297Sandreas.sandberg@arm.com 83111297Sandreas.sandberg@arm.comInterrupts: 83211297Sandreas.sandberg@arm.com 0- 15: Software generated interrupts (SGIs) 83311297Sandreas.sandberg@arm.com 16- 31: On-chip private peripherals (PPIs) 83411297Sandreas.sandberg@arm.com 25 : vgic 83511297Sandreas.sandberg@arm.com 26 : generic_timer (hyp) 83611297Sandreas.sandberg@arm.com 27 : generic_timer (virt) 83711297Sandreas.sandberg@arm.com 28 : Reserved (Legacy FIQ) 83811297Sandreas.sandberg@arm.com 29 : generic_timer (phys, sec) 83911297Sandreas.sandberg@arm.com 30 : generic_timer (phys, non-sec) 84011297Sandreas.sandberg@arm.com 31 : Reserved (Legacy IRQ) 84111297Sandreas.sandberg@arm.com 32- 95: Mother board peripherals (SPIs) 84211297Sandreas.sandberg@arm.com 32 : Reserved (SP805) 84311297Sandreas.sandberg@arm.com 33 : Reserved (IOFPGA SW int) 84411297Sandreas.sandberg@arm.com 34-35: Reserved (SP804) 84511297Sandreas.sandberg@arm.com 36 : RTC 84611297Sandreas.sandberg@arm.com 37-40: uart0-uart3 84711297Sandreas.sandberg@arm.com 41-42: Reserved (PL180) 84811297Sandreas.sandberg@arm.com 43 : Reserved (AACI) 84911297Sandreas.sandberg@arm.com 44-45: kmi0-kmi1 85011297Sandreas.sandberg@arm.com 46 : Reserved (CLCD) 85111297Sandreas.sandberg@arm.com 47 : Reserved (Ethernet) 85211297Sandreas.sandberg@arm.com 48 : Reserved (USB) 85311297Sandreas.sandberg@arm.com 95-255: On-chip interrupt sources (we use these for 85411297Sandreas.sandberg@arm.com gem5-specific devices, SPIs) 85511297Sandreas.sandberg@arm.com 95 : HDLCD 85611297Sandreas.sandberg@arm.com 96- 98: GPU (reserved) 85711297Sandreas.sandberg@arm.com 100-103: PCI 85811297Sandreas.sandberg@arm.com 256-319: MSI frame 0 (gem5-specific, SPIs) 85911297Sandreas.sandberg@arm.com 320-511: Unused 86011297Sandreas.sandberg@arm.com 86111297Sandreas.sandberg@arm.com """ 86211297Sandreas.sandberg@arm.com 86311297Sandreas.sandberg@arm.com # Everything above 2GiB is memory 86411297Sandreas.sandberg@arm.com _mem_regions = [(Addr('2GB'), Addr('510GB'))] 86511297Sandreas.sandberg@arm.com 86611297Sandreas.sandberg@arm.com _off_chip_ranges = [ 86711297Sandreas.sandberg@arm.com # CS1-CS5 86811297Sandreas.sandberg@arm.com AddrRange(0x0c000000, 0x1fffffff), 86911297Sandreas.sandberg@arm.com # External AXI interface (PCI) 87011297Sandreas.sandberg@arm.com AddrRange(0x2f000000, 0x7fffffff), 87111297Sandreas.sandberg@arm.com ] 87211297Sandreas.sandberg@arm.com 87311297Sandreas.sandberg@arm.com # Platform control device (off-chip) 87411297Sandreas.sandberg@arm.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 87511297Sandreas.sandberg@arm.com idreg=0x02250000, pio_addr=0x1c010000) 87611297Sandreas.sandberg@arm.com mcc = VExpressMCC() 87711297Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 87811297Sandreas.sandberg@arm.com 87911297Sandreas.sandberg@arm.com ### On-chip devices ### 88011297Sandreas.sandberg@arm.com gic = Pl390(dist_addr=0x2c001000, cpu_addr=0x2c002000, it_lines=512) 88111297Sandreas.sandberg@arm.com vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 88211297Sandreas.sandberg@arm.com gicv2m = Gicv2m() 88311297Sandreas.sandberg@arm.com gicv2m.frames = [ 88411297Sandreas.sandberg@arm.com Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000), 88511297Sandreas.sandberg@arm.com ] 88611297Sandreas.sandberg@arm.com 88711297Sandreas.sandberg@arm.com generic_timer = GenericTimer(int_phys=29, int_virt=27) 88811297Sandreas.sandberg@arm.com 88911297Sandreas.sandberg@arm.com hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 89011297Sandreas.sandberg@arm.com pio_addr=0x2b000000, int_num=95) 89111297Sandreas.sandberg@arm.com 89211297Sandreas.sandberg@arm.com def _on_chip_devices(self): 89311297Sandreas.sandberg@arm.com return [ 89411297Sandreas.sandberg@arm.com self.gic, self.vgic, self.gicv2m, 89511297Sandreas.sandberg@arm.com self.hdlcd, 89611297Sandreas.sandberg@arm.com self.generic_timer, 89711297Sandreas.sandberg@arm.com ] 89811297Sandreas.sandberg@arm.com 89911297Sandreas.sandberg@arm.com ### Off-chip devices ### 90011297Sandreas.sandberg@arm.com uart0 = Pl011(pio_addr=0x1c090000, int_num=37) 90111297Sandreas.sandberg@arm.com 90211297Sandreas.sandberg@arm.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 90311297Sandreas.sandberg@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 90411297Sandreas.sandberg@arm.com 90511297Sandreas.sandberg@arm.com rtc = PL031(pio_addr=0x1c170000, int_num=36) 90611297Sandreas.sandberg@arm.com 90711297Sandreas.sandberg@arm.com ### gem5-specific off-chip devices ### 90811297Sandreas.sandberg@arm.com pci_host = GenericArmPciHost( 90911297Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 91011297Sandreas.sandberg@arm.com pci_pio_base=0x2f000000, 91111297Sandreas.sandberg@arm.com int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4) 91211297Sandreas.sandberg@arm.com 91311297Sandreas.sandberg@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x10000000) 91411297Sandreas.sandberg@arm.com 91511297Sandreas.sandberg@arm.com 91611297Sandreas.sandberg@arm.com def _off_chip_devices(self): 91711297Sandreas.sandberg@arm.com return [ 91811297Sandreas.sandberg@arm.com self.realview_io, 91911297Sandreas.sandberg@arm.com self.uart0, 92011297Sandreas.sandberg@arm.com self.kmi0, self.kmi1, 92111297Sandreas.sandberg@arm.com self.rtc, 92211297Sandreas.sandberg@arm.com self.pci_host, 92311297Sandreas.sandberg@arm.com self.energy_ctrl, 92411297Sandreas.sandberg@arm.com ] 92511297Sandreas.sandberg@arm.com 92611297Sandreas.sandberg@arm.com def attachPciDevice(self, device, bus): 92711297Sandreas.sandberg@arm.com device.host = self.pci_host 92811297Sandreas.sandberg@arm.com device.pio = bus.master 92911297Sandreas.sandberg@arm.com device.dma = bus.slave 93011297Sandreas.sandberg@arm.com 93111297Sandreas.sandberg@arm.com def setupBootLoader(self, mem_bus, cur_sys, loc): 93211595Sandreas.sandberg@arm.com self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'), 93311595Sandreas.sandberg@arm.com conf_table_reported=False) 93411297Sandreas.sandberg@arm.com self.nvmem.port = mem_bus.master 93511297Sandreas.sandberg@arm.com cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ] 93611297Sandreas.sandberg@arm.com cur_sys.atags_addr = 0x8000000 93711297Sandreas.sandberg@arm.com cur_sys.load_addr_mask = 0xfffffff 93811297Sandreas.sandberg@arm.com cur_sys.load_offset = 0x80000000 939