RealView.py revision 10356
110353SGeoffrey.Blake@arm.com# Copyright (c) 2009-2014 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 424486SN/A 433630SN/Afrom m5.params import * 443630SN/Afrom m5.proxy import * 457587SAli.Saidi@arm.comfrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 468525SAli.Saidi@ARM.comfrom Pci import PciConfigAll 4710353SGeoffrey.Blake@arm.comfrom Ethernet import NSGigE, IGbE_igb, IGbE_e1000 488212SAli.Saidi@ARM.comfrom Ide import * 495478SN/Afrom Platform import Platform 505478SN/Afrom Terminal import Terminal 517584SAli.Saidi@arm.comfrom Uart import Uart 528931Sandreas.hansson@arm.comfrom SimpleMemory import SimpleMemory 539525SAndreas.Sandberg@ARM.comfrom Gic import * 543630SN/A 559806Sstever@gmail.comclass AmbaPioDevice(BasicPioDevice): 569806Sstever@gmail.com type = 'AmbaPioDevice' 577584SAli.Saidi@arm.com abstract = True 589338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 597584SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 603898SN/A 619806Sstever@gmail.comclass AmbaIntDevice(AmbaPioDevice): 627950SAli.Saidi@ARM.com type = 'AmbaIntDevice' 637950SAli.Saidi@ARM.com abstract = True 649338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 659525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 667950SAli.Saidi@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 677950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 687950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 697950SAli.Saidi@ARM.com 707587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 717587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 727587SAli.Saidi@arm.com abstract = True 739338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 747753SWilliam.Wang@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 757753SWilliam.Wang@arm.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 769525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 777753SWilliam.Wang@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 787587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 797587SAli.Saidi@arm.com 808282SAli.Saidi@ARM.comclass A9SCU(BasicPioDevice): 818282SAli.Saidi@ARM.com type = 'A9SCU' 829338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/a9scu.hh" 838282SAli.Saidi@ARM.com 847584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 857584SAli.Saidi@arm.com type = 'RealViewCtrl' 869338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 878524SAli.Saidi@ARM.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 888524SAli.Saidi@ARM.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 898299Schander.sudanthi@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 907584SAli.Saidi@arm.com 9110037SARM gem5 Developersclass VGic(PioDevice): 9210037SARM gem5 Developers type = 'VGic' 9310037SARM gem5 Developers cxx_header = "dev/arm/vgic.hh" 9410037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 9510037SARM gem5 Developers platform = Param.Platform(Parent.any, "Platform this device is part of.") 9610037SARM gem5 Developers vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 9710037SARM gem5 Developers hv_addr = Param.Addr(0, "Address for hv control") 9810037SARM gem5 Developers pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 9910037SARM gem5 Developers # The number of list registers is not currently configurable at runtime. 10010037SARM gem5 Developers ppint = Param.UInt32("HV maintenance interrupt number") 10110037SARM gem5 Developers 1029806Sstever@gmail.comclass AmbaFake(AmbaPioDevice): 1037584SAli.Saidi@arm.com type = 'AmbaFake' 1049338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_fake.hh" 1057584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 1067584SAli.Saidi@arm.com amba_id = 0; 1077584SAli.Saidi@arm.com 1087584SAli.Saidi@arm.comclass Pl011(Uart): 1097584SAli.Saidi@arm.com type = 'Pl011' 1109338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl011.hh" 1119525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1127584SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 1137584SAli.Saidi@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 1147584SAli.Saidi@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 1157584SAli.Saidi@arm.com 1169806Sstever@gmail.comclass Sp804(AmbaPioDevice): 1177584SAli.Saidi@arm.com type = 'Sp804' 1189338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_sp804.hh" 1199525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1207584SAli.Saidi@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 1217584SAli.Saidi@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 1227584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 1237584SAli.Saidi@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 1247584SAli.Saidi@arm.com amba_id = 0x00141804 1257584SAli.Saidi@arm.com 1268512Sgeoffrey.blake@arm.comclass CpuLocalTimer(BasicPioDevice): 1278512Sgeoffrey.blake@arm.com type = 'CpuLocalTimer' 1289338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_cpulocal.hh" 1299525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1308512Sgeoffrey.blake@arm.com int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 1318512Sgeoffrey.blake@arm.com int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 1328512Sgeoffrey.blake@arm.com 13310037SARM gem5 Developersclass GenericTimer(SimObject): 13410037SARM gem5 Developers type = 'GenericTimer' 13510037SARM gem5 Developers cxx_header = "dev/arm/generic_timer.hh" 13610037SARM gem5 Developers system = Param.System(Parent.any, "system") 13710037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 13810037SARM gem5 Developers int_num = Param.UInt32("Interrupt number used per-cpu to GIC") 13910037SARM gem5 Developers # @todo: for now only one timer per CPU is supported, which is the 14010037SARM gem5 Developers # normal behaviour when Security and Virt. extensions are disabled. 14110037SARM gem5 Developers 1428870SAli.Saidi@ARM.comclass PL031(AmbaIntDevice): 1438870SAli.Saidi@ARM.com type = 'PL031' 1449338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rtc_pl031.hh" 1458870SAli.Saidi@ARM.com time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 1468870SAli.Saidi@ARM.com amba_id = 0x00341031 1478870SAli.Saidi@ARM.com 1487950SAli.Saidi@ARM.comclass Pl050(AmbaIntDevice): 1497754SWilliam.Wang@arm.com type = 'Pl050' 1509338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/kmi.hh" 1519330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 1527950SAli.Saidi@ARM.com is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 1537950SAli.Saidi@ARM.com int_delay = '1us' 1547754SWilliam.Wang@arm.com amba_id = 0x00141050 1557754SWilliam.Wang@arm.com 1567753SWilliam.Wang@arm.comclass Pl111(AmbaDmaDevice): 1577753SWilliam.Wang@arm.com type = 'Pl111' 1589338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl111.hh" 1599394Sandreas.hansson@arm.com pixel_clock = Param.Clock('24MHz', "Pixel clock") 1609330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 1617753SWilliam.Wang@arm.com amba_id = 0x00141111 1629939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 1639939Sdam.sunwoo@arm.com 1647753SWilliam.Wang@arm.com 1659646SChris.Emmons@arm.comclass HDLcd(AmbaDmaDevice): 1669646SChris.Emmons@arm.com type = 'HDLcd' 1679646SChris.Emmons@arm.com cxx_header = "dev/arm/hdlcd.hh" 16810187SChris.Emmons@arm.com # For reference, 1024x768MR-16@60 ~= 56 MHz 16910187SChris.Emmons@arm.com # 1920x1080MR-16@60 ~= 137 MHz 17010187SChris.Emmons@arm.com # 3840x2160MR-16@60 ~= 533 MHz 17110187SChris.Emmons@arm.com # Match against the resolution selected in the Linux DTS/DTB file. 17210187SChris.Emmons@arm.com pixel_clock = Param.Clock('137MHz', "Clock frequency of the pixel clock " 17310187SChris.Emmons@arm.com "(i.e. PXLREFCLK / OSCCLK 5") 1749646SChris.Emmons@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 1759646SChris.Emmons@arm.com "display") 1769646SChris.Emmons@arm.com amba_id = 0x00141000 1779939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 1789646SChris.Emmons@arm.com 1797584SAli.Saidi@arm.comclass RealView(Platform): 1807584SAli.Saidi@arm.com type = 'RealView' 1819338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/realview.hh" 1823630SN/A system = Param.System(Parent.any, "system") 18310356SAli.Saidi@ARM.com pci_io_base = Param.Addr(0, "Base address of PCI IO Space") 1848525SAli.Saidi@ARM.com pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 18510356SAli.Saidi@ARM.com pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access" 18610356SAli.Saidi@ARM.com " be compatible with the pci-generic-host or the legacy host bridge?") 1878870SAli.Saidi@ARM.com mem_start_addr = Param.Addr(0, "Start address of main memory") 1888870SAli.Saidi@ARM.com max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") 1898870SAli.Saidi@ARM.com 19010353SGeoffrey.Blake@arm.com def attachPciDevices(self): 19110353SGeoffrey.Blake@arm.com pass 19210353SGeoffrey.Blake@arm.com 19310353SGeoffrey.Blake@arm.com def enableMSIX(self): 19410353SGeoffrey.Blake@arm.com pass 19510353SGeoffrey.Blake@arm.com 19610353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 19710353SGeoffrey.Blake@arm.com pass 19810353SGeoffrey.Blake@arm.com 19910353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 20010353SGeoffrey.Blake@arm.com pass 20110353SGeoffrey.Blake@arm.com 2028870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 2039835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 2049835Sandreas.hansson@arm.com conf_table_reported = False) 2058870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 2068870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot.arm') 20710037SARM gem5 Developers cur_sys.atags_addr = 0x100 20810037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 20910037SARM gem5 Developers cur_sys.load_offset = 0 2108870SAli.Saidi@ARM.com 2113630SN/A 2127753SWilliam.Wang@arm.com# Reference for memory map and interrupt number 2137753SWilliam.Wang@arm.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 2147753SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 2157584SAli.Saidi@arm.comclass RealViewPBX(RealView): 2167584SAli.Saidi@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 2177584SAli.Saidi@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000) 2189525SAndreas.Sandberg@ARM.com gic = Pl390() 2197584SAli.Saidi@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 2207584SAli.Saidi@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 2218512Sgeoffrey.blake@arm.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 2227753SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=55) 2237754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 2247950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 2258282SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0x1f000000) 2268525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 2278212SAli.Saidi@ARM.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 2288212SAli.Saidi@ARM.com BAR0 = 0x18000000, BAR0Size = '16B', 2298212SAli.Saidi@ARM.com BAR1 = 0x18000100, BAR1Size = '1B', 2308212SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 2318212SAli.Saidi@ARM.com 2327584SAli.Saidi@arm.com 2337731SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 2348461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 2358461SAli.Saidi@ARM.com fake_mem=True) 2367696SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0x10030000) 2377696SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 2387696SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 2397696SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 2407696SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 2417696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 2427696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 2437696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 2447696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 2457696SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 2467696SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 2477696SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 2487696SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 2497696SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 2508906Skoansin.tan@gmail.com rtc = PL031(pio_addr=0x10017000, int_num=42) 2517696SAli.Saidi@ARM.com 2527696SAli.Saidi@ARM.com 2538713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 2548713Sandreas.hansson@arm.com # ranges for the bridge 2558713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 2568839Sandreas.hansson@arm.com self.gic.pio = bus.master 2578839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 2588839Sandreas.hansson@arm.com self.a9scu.pio = bus.master 2598839Sandreas.hansson@arm.com self.local_cpu_timer.pio = bus.master 2608713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 2618713Sandreas.hansson@arm.com # (gic, l2x0, a9scu, local_cpu_timer) 2628713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 2638713Sandreas.hansson@arm.com self.a9scu.pio_addr - 1), 2648870SAli.Saidi@ARM.com AddrRange(self.flash_fake.pio_addr, 2658870SAli.Saidi@ARM.com self.flash_fake.pio_addr + \ 2668870SAli.Saidi@ARM.com self.flash_fake.pio_size - 1)] 2677696SAli.Saidi@ARM.com 26810353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 26910353SGeoffrey.Blake@arm.com # to be "close" to the cores. 27010353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 27110353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 27210353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 27310353SGeoffrey.Blake@arm.com self.a9scu.clkdomain = clkdomain 27410353SGeoffrey.Blake@arm.com self.local_cpu_timer.clk_domain = clkdomain 27510353SGeoffrey.Blake@arm.com 2767696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 2777696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 2787696SAli.Saidi@ARM.com # System level. 2797696SAli.Saidi@ARM.com def attachIO(self, bus): 2808839Sandreas.hansson@arm.com self.uart.pio = bus.master 2818839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 2828839Sandreas.hansson@arm.com self.timer0.pio = bus.master 2838839Sandreas.hansson@arm.com self.timer1.pio = bus.master 2848839Sandreas.hansson@arm.com self.clcd.pio = bus.master 2858839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 2868839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 2878839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 2888839Sandreas.hansson@arm.com self.cf_ctrl.pio = bus.master 2898839Sandreas.hansson@arm.com self.cf_ctrl.config = bus.master 2908839Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.slave 2918839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 2928839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 2938839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 2948839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 2958839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 2968839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 2978839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 2988839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 2998839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 3008839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 3018839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 3028839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 3038839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 3048839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 3058906Skoansin.tan@gmail.com self.rtc.pio = bus.master 3068839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 3077696SAli.Saidi@ARM.com 30810353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 30910353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 31010353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 31110353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 31210353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 31310353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 31410353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 31510353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 31610353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 31710353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 31810353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 31910353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 32010353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 32110353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 32210353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 32310353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 32410353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 32510353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 32610353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 32710353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 32810353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 32910353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 33010353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 33110353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 33210353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 33310353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 33410353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 33510353SGeoffrey.Blake@arm.com 3367754SWilliam.Wang@arm.com# Reference for memory map and interrupt number 3377754SWilliam.Wang@arm.com# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 3387754SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 3397696SAli.Saidi@ARM.comclass RealViewEB(RealView): 3407696SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x10009000, int_num=44) 34110353SGeoffrey.Blake@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) 3429525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 3437696SAli.Saidi@ARM.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 3447696SAli.Saidi@ARM.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 3457754SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=23) 3467754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 3477950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 3487696SAli.Saidi@ARM.com 3497696SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 3508461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 3518461SAli.Saidi@ARM.com fake_mem=True) 3527584SAli.Saidi@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 3537584SAli.Saidi@arm.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 3547584SAli.Saidi@arm.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 3557584SAli.Saidi@arm.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 3568299Schander.sudanthi@arm.com smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 3577584SAli.Saidi@arm.com smc_fake = AmbaFake(pio_addr=0x100e1000) 3587584SAli.Saidi@arm.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 3597584SAli.Saidi@arm.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 3607584SAli.Saidi@arm.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 3617584SAli.Saidi@arm.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 3627584SAli.Saidi@arm.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 3637584SAli.Saidi@arm.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 3647584SAli.Saidi@arm.com sci_fake = AmbaFake(pio_addr=0x1000e000) 3657584SAli.Saidi@arm.com aaci_fake = AmbaFake(pio_addr=0x10004000) 3667584SAli.Saidi@arm.com mmc_fake = AmbaFake(pio_addr=0x10005000) 3677584SAli.Saidi@arm.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 3687584SAli.Saidi@arm.com 3697584SAli.Saidi@arm.com 3707584SAli.Saidi@arm.com 3718713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 3728713Sandreas.hansson@arm.com # ranges for the bridge 3738713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 3748839Sandreas.hansson@arm.com self.gic.pio = bus.master 3758839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 3768713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 3778713Sandreas.hansson@arm.com # (gic, l2x0) 3788713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 3798713Sandreas.hansson@arm.com self.gic.cpu_addr - 1), 3808713Sandreas.hansson@arm.com AddrRange(self.flash_fake.pio_addr, Addr.max)] 3814104SN/A 38210353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 38310353SGeoffrey.Blake@arm.com # to be "close" to the cores. 38410353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 38510353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 38610353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 38710353SGeoffrey.Blake@arm.com 3883630SN/A # Attach I/O devices to specified bus object. Can't do this 3893630SN/A # earlier, since the bus object itself is typically defined at the 3903630SN/A # System level. 3913630SN/A def attachIO(self, bus): 3928839Sandreas.hansson@arm.com self.uart.pio = bus.master 3938839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 3948839Sandreas.hansson@arm.com self.timer0.pio = bus.master 3958839Sandreas.hansson@arm.com self.timer1.pio = bus.master 3968839Sandreas.hansson@arm.com self.clcd.pio = bus.master 3978839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 3988839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 3998839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 4008839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 4018839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 4028839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 4038839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 4048839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 4058839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 4068839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 4078839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 4088839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 4098839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 4108839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 4118839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 4128839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 4138839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 4148839Sandreas.hansson@arm.com self.rtc_fake.pio = bus.master 4158839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 4168839Sandreas.hansson@arm.com self.smcreg_fake.pio = bus.master 4177584SAli.Saidi@arm.com 41810353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 41910353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 42010353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 42110353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 42210353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 42310353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 42410353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 42510353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 42610353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 42710353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 42810353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 42910353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 43010353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 43110353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 43210353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 43310353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 43410353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 43510353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 43610353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 43710353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 43810353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 43910353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 44010353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 44110353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 44210353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 44310353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 44410353SGeoffrey.Blake@arm.com self.smcreg_fake.clk_domain = clkdomain 44510353SGeoffrey.Blake@arm.com 4468870SAli.Saidi@ARM.comclass VExpress_EMM(RealView): 4478870SAli.Saidi@ARM.com mem_start_addr = '2GB' 4488870SAli.Saidi@ARM.com max_mem_size = '2GB' 4499052Sgeoffrey.blake@arm.com pci_cfg_base = 0x30000000 4508870SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x1c090000, int_num=37) 45110353SGeoffrey.Blake@arm.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \ 45210353SGeoffrey.Blake@arm.com idreg=0x02250000, pio_addr=0x1C010000) 4539525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 4548870SAli.Saidi@ARM.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 45510037SARM gem5 Developers generic_timer = GenericTimer(int_num=29) 4569185SAli.Saidi@ARM.com timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 4579185SAli.Saidi@ARM.com timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 4588870SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 4599646SChris.Emmons@arm.com hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117) 4608870SAli.Saidi@ARM.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 4619387SChris.Emmons@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 46210037SARM gem5 Developers vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 4638870SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 4648870SAli.Saidi@ARM.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 4658870SAli.Saidi@ARM.com BAR0 = 0x1C1A0000, BAR0Size = '256B', 4668870SAli.Saidi@ARM.com BAR1 = 0x1C1A0100, BAR1Size = '4096B', 4678870SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 4689052Sgeoffrey.blake@arm.com 4699052Sgeoffrey.blake@arm.com pciconfig = PciConfigAll(size='256MB') 4709835Sandreas.hansson@arm.com vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 4719835Sandreas.hansson@arm.com conf_table_reported = False) 4728870SAli.Saidi@ARM.com rtc = PL031(pio_addr=0x1C170000, int_num=36) 4738870SAli.Saidi@ARM.com 4748870SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 4758870SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 4768870SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 4778870SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 4788870SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 4798870SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 4808870SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x1C040000) 4818870SAli.Saidi@ARM.com lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 4828870SAli.Saidi@ARM.com usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 4838870SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x1c050000) 4848870SAli.Saidi@ARM.com 48510353SGeoffrey.Blake@arm.com # Attach any PCI devices that are supported 48610353SGeoffrey.Blake@arm.com def attachPciDevices(self): 48710353SGeoffrey.Blake@arm.com self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 48810353SGeoffrey.Blake@arm.com InterruptLine=1, InterruptPin=1) 48910353SGeoffrey.Blake@arm.com self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 49010353SGeoffrey.Blake@arm.com InterruptLine=2, InterruptPin=2) 49110353SGeoffrey.Blake@arm.com 49210353SGeoffrey.Blake@arm.com def enableMSIX(self): 49310353SGeoffrey.Blake@arm.com self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 49410353SGeoffrey.Blake@arm.com self.gicv2m = Gicv2m() 49510353SGeoffrey.Blake@arm.com self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 49610353SGeoffrey.Blake@arm.com 4978870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 4989835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('64MB'), 4999835Sandreas.hansson@arm.com conf_table_reported = False) 5008870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 5018870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot_emm.arm') 50210037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 50310037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 50410037SARM gem5 Developers cur_sys.load_offset = 0x80000000 5058870SAli.Saidi@ARM.com 5068870SAli.Saidi@ARM.com # Attach I/O devices that are on chip and also set the appropriate 5078870SAli.Saidi@ARM.com # ranges for the bridge 5088870SAli.Saidi@ARM.com def attachOnChipIO(self, bus, bridge): 5098870SAli.Saidi@ARM.com self.gic.pio = bus.master 5108870SAli.Saidi@ARM.com self.local_cpu_timer.pio = bus.master 51110353SGeoffrey.Blake@arm.com if hasattr(self, "gicv2m"): 51210353SGeoffrey.Blake@arm.com self.gicv2m.pio = bus.master 5139646SChris.Emmons@arm.com self.hdlcd.dma = bus.slave 5148870SAli.Saidi@ARM.com # Bridge ranges based on excluding what is part of on-chip I/O 5158870SAli.Saidi@ARM.com # (gic, a9scu) 5168870SAli.Saidi@ARM.com bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 5179646SChris.Emmons@arm.com AddrRange(0x2B000000, size='4MB'), 5188870SAli.Saidi@ARM.com AddrRange(0x30000000, size='256MB'), 5199073SAli.Saidi@ARM.com AddrRange(0x40000000, size='512MB'), 5208870SAli.Saidi@ARM.com AddrRange(0x18000000, size='64MB'), 5218870SAli.Saidi@ARM.com AddrRange(0x1C000000, size='64MB')] 52210037SARM gem5 Developers self.vgic.pio = bus.master 52310037SARM gem5 Developers 5248870SAli.Saidi@ARM.com 52510353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 52610353SGeoffrey.Blake@arm.com # to be "close" to the cores. 52710353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 52810353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 52910353SGeoffrey.Blake@arm.com if hasattr(self, "gicv2m"): 53010353SGeoffrey.Blake@arm.com self.gicv2m.clk_domain = clkdomain 53110353SGeoffrey.Blake@arm.com self.hdlcd.clk_domain = clkdomain 53210353SGeoffrey.Blake@arm.com self.vgic.clk_domain = clkdomain 53310353SGeoffrey.Blake@arm.com 53410353SGeoffrey.Blake@arm.com # Attach I/O devices to specified bus object. Done here 53510353SGeoffrey.Blake@arm.com # as the specified bus to connect to may not always be fixed. 5368870SAli.Saidi@ARM.com def attachIO(self, bus): 5378870SAli.Saidi@ARM.com self.uart.pio = bus.master 5388870SAli.Saidi@ARM.com self.realview_io.pio = bus.master 5398870SAli.Saidi@ARM.com self.timer0.pio = bus.master 5408870SAli.Saidi@ARM.com self.timer1.pio = bus.master 5418870SAli.Saidi@ARM.com self.clcd.pio = bus.master 5428870SAli.Saidi@ARM.com self.clcd.dma = bus.slave 5439646SChris.Emmons@arm.com self.hdlcd.pio = bus.master 5448870SAli.Saidi@ARM.com self.kmi0.pio = bus.master 5458870SAli.Saidi@ARM.com self.kmi1.pio = bus.master 5468870SAli.Saidi@ARM.com self.cf_ctrl.pio = bus.master 5478872Ssaidi@eecs.umich.edu self.cf_ctrl.dma = bus.slave 5488870SAli.Saidi@ARM.com self.cf_ctrl.config = bus.master 5498870SAli.Saidi@ARM.com self.rtc.pio = bus.master 5508870SAli.Saidi@ARM.com bus.use_default_range = True 5518870SAli.Saidi@ARM.com self.vram.port = bus.master 5529052Sgeoffrey.blake@arm.com self.pciconfig.pio = bus.default 5538870SAli.Saidi@ARM.com 5548870SAli.Saidi@ARM.com self.l2x0_fake.pio = bus.master 5558870SAli.Saidi@ARM.com self.uart1_fake.pio = bus.master 5568870SAli.Saidi@ARM.com self.uart2_fake.pio = bus.master 5578870SAli.Saidi@ARM.com self.uart3_fake.pio = bus.master 5588870SAli.Saidi@ARM.com self.sp810_fake.pio = bus.master 5598870SAli.Saidi@ARM.com self.watchdog_fake.pio = bus.master 5608870SAli.Saidi@ARM.com self.aaci_fake.pio = bus.master 5618870SAli.Saidi@ARM.com self.lan_fake.pio = bus.master 5628870SAli.Saidi@ARM.com self.usb_fake.pio = bus.master 5638870SAli.Saidi@ARM.com self.mmc_fake.pio = bus.master 5648870SAli.Saidi@ARM.com 56510353SGeoffrey.Blake@arm.com # Try to attach the I/O if it exists 56610353SGeoffrey.Blake@arm.com try: 56710353SGeoffrey.Blake@arm.com self.ide.pio = bus.master 56810353SGeoffrey.Blake@arm.com self.ide.config = bus.master 56910353SGeoffrey.Blake@arm.com self.ide.dma = bus.slave 57010353SGeoffrey.Blake@arm.com self.ethernet.pio = bus.master 57110353SGeoffrey.Blake@arm.com self.ethernet.config = bus.master 57210353SGeoffrey.Blake@arm.com self.ethernet.dma = bus.slave 57310353SGeoffrey.Blake@arm.com except: 57410353SGeoffrey.Blake@arm.com pass 57510353SGeoffrey.Blake@arm.com 57610353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 57710353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 57810353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 57910353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 58010353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 58110353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 58210353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 58310353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 58410353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 58510353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 58610353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 58710353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 58810353SGeoffrey.Blake@arm.com self.vram.clk_domain = clkdomain 58910353SGeoffrey.Blake@arm.com self.pciconfig.clk_domain = clkdomain 59010353SGeoffrey.Blake@arm.com 59110353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 59210353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 59310353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 59410353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 59510353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 59610353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 59710353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 59810353SGeoffrey.Blake@arm.com self.lan_fake.clk_domain = clkdomain 59910353SGeoffrey.Blake@arm.com self.usb_fake.clk_domain = clkdomain 60010353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 60110353SGeoffrey.Blake@arm.com 60210037SARM gem5 Developersclass VExpress_EMM64(VExpress_EMM): 60310356SAli.Saidi@ARM.com pci_io_base = 0x2f000000 60410356SAli.Saidi@ARM.com pci_cfg_gen_offsets = True 60510037SARM gem5 Developers def setupBootLoader(self, mem_bus, cur_sys, loc): 60610037SARM gem5 Developers self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 60710037SARM gem5 Developers self.nvmem.port = mem_bus.master 60810037SARM gem5 Developers cur_sys.boot_loader = loc('boot_emm.arm64') 60910037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 61010037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 61110037SARM gem5 Developers cur_sys.load_offset = 0x80000000 61210037SARM gem5 Developers 61310037SARM gem5 Developers 614