Gic.py revision 13877:a4ac726b549d 
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36# Authors: Andreas Sandberg
37
38from m5.params import *
39from m5.proxy import *
40from m5.util.fdthelper import *
41from m5.SimObject import SimObject
42
43from m5.objects.Device import PioDevice
44from m5.objects.Platform import Platform
45
46class BaseGic(PioDevice):
47    type = 'BaseGic'
48    abstract = True
49    cxx_header = "dev/arm/base_gic.hh"
50
51    platform = Param.Platform(Parent.any, "Platform this device is part of.")
52
53    gicd_iidr = Param.UInt32(0,
54        "Distributor Implementer Identification Register")
55    gicd_pidr = Param.UInt32(0,
56        "Peripheral Identification Register")
57    gicc_iidr = Param.UInt32(0,
58        "CPU Interface Identification Register")
59    gicv_iidr = Param.UInt32(0,
60        "VM CPU Interface Identification Register")
61
62class ArmInterruptPin(SimObject):
63    type = 'ArmInterruptPin'
64    cxx_header = "dev/arm/base_gic.hh"
65    cxx_class = "ArmInterruptPinGen"
66    abstract = True
67
68    platform = Param.Platform(Parent.any, "Platform with interrupt controller")
69    num = Param.UInt32("Interrupt number in GIC")
70
71class ArmSPI(ArmInterruptPin):
72    type = 'ArmSPI'
73    cxx_header = "dev/arm/base_gic.hh"
74    cxx_class = "ArmSPIGen"
75
76class ArmPPI(ArmInterruptPin):
77    type = 'ArmPPI'
78    cxx_header = "dev/arm/base_gic.hh"
79    cxx_class = "ArmPPIGen"
80
81class GicV2(BaseGic):
82    type = 'GicV2'
83    cxx_header = "dev/arm/gic_v2.hh"
84
85    dist_addr = Param.Addr("Address for distributor")
86    cpu_addr = Param.Addr("Address for cpu")
87    cpu_size = Param.Addr(0x2000, "Size of cpu register bank")
88    dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
89    cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
90    int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
91    it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
92    gem5_extensions = Param.Bool(False, "Enable gem5 extensions")
93
94class Gic400(GicV2):
95    """
96    As defined in:
97    "ARM Generic Interrupt Controller Architecture" version 2.0
98    "CoreLink GIC-400 Generic Interrupt Controller" revision r0p1
99    """
100    gicd_pidr = 0x002bb490
101    gicd_iidr = 0x0200143B
102    gicc_iidr = 0x0202143B
103
104    # gicv_iidr same as gicc_idr
105    gicv_iidr = gicc_iidr
106
107class Gicv2mFrame(SimObject):
108    type = 'Gicv2mFrame'
109    cxx_header = "dev/arm/gic_v2m.hh"
110    spi_base = Param.UInt32(0x0, "Frame SPI base number");
111    spi_len = Param.UInt32(0x0, "Frame SPI total number");
112    addr = Param.Addr("Address for frame PIO")
113
114class Gicv2m(PioDevice):
115    type = 'Gicv2m'
116    cxx_header = "dev/arm/gic_v2m.hh"
117
118    pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
119    gic = Param.BaseGic(Parent.any, "Gic on which to trigger interrupts")
120    frames = VectorParam.Gicv2mFrame([], "Power of two number of frames")
121
122class VGic(PioDevice):
123    type = 'VGic'
124    cxx_header = "dev/arm/vgic.hh"
125    gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
126    platform = Param.Platform(Parent.any, "Platform this device is part of.")
127    vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
128    hv_addr = Param.Addr(0, "Address for hv control")
129    pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
130   # The number of list registers is not currently configurable at runtime.
131    maint_int = Param.UInt32("HV maintenance interrupt number")
132
133    # gicv_iidr same as gicc_idr
134    gicv_iidr = Param.UInt32(Self.gic.gicc_iidr,
135        "VM CPU Interface Identification Register")
136
137    def generateDeviceTree(self, state):
138        gic = self.gic.unproxy(self)
139
140        node = FdtNode("interrupt-controller")
141        node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic",
142                               "arm,cortex-a9-gic"])
143        node.append(FdtPropertyWords("#interrupt-cells", [3]))
144        node.append(FdtPropertyWords("#address-cells", [0]))
145        node.append(FdtProperty("interrupt-controller"))
146
147        regs = (
148            state.addrCells(gic.dist_addr) +
149            state.sizeCells(0x1000) +
150            state.addrCells(gic.cpu_addr) +
151            state.sizeCells(0x1000) +
152            state.addrCells(self.hv_addr) +
153            state.sizeCells(0x2000) +
154            state.addrCells(self.vcpu_addr) +
155            state.sizeCells(0x2000) )
156
157        node.append(FdtPropertyWords("reg", regs))
158        node.append(FdtPropertyWords("interrupts",
159                                     [1, int(self.maint_int)-16, 0xf04]))
160
161        node.appendPhandle(gic)
162
163        yield node
164
165class Gicv3(BaseGic):
166    type = 'Gicv3'
167    cxx_header = "dev/arm/gic_v3.hh"
168
169    dist_addr = Param.Addr(0x2c000000, "Address for distributor")
170    dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
171    redist_addr = Param.Addr(0x2c010000, "Address for redistributors")
172    redist_pio_delay = Param.Latency('10ns',
173            "Delay for PIO r/w to redistributors")
174    it_lines = Param.UInt32(1020,
175            "Number of interrupt lines supported (max = 1020)")
176
177    maint_int = Param.ArmInterruptPin(
178        "HV maintenance interrupt."
179        "ARM strongly recommends that maintenance interrupts "
180        "are configured to use INTID 25 (PPI Interrupt).")
181
182    cpu_max = Param.Unsigned(256,
183        "Maximum number of PE. This is affecting the maximum number of "
184        "redistributors")
185