Gic.py revision 14173
12330SN/A# Copyright (c) 2012-2013, 2017-2019 ARM Limited 213610Sgiacomo.gabrielli@arm.com# All rights reserved. 39920Syasuko.eckert@amd.com# 48733Sgeoffrey.blake@arm.com# The license below extends only to copyright in the software and shall 58733Sgeoffrey.blake@arm.com# not be construed as granting a license to any other intellectual 68733Sgeoffrey.blake@arm.com# property including but not limited to intellectual property relating 78733Sgeoffrey.blake@arm.com# to a hardware implementation of the functionality of the software 88733Sgeoffrey.blake@arm.com# licensed hereunder. You may use the software subject to the license 98733Sgeoffrey.blake@arm.com# terms below provided that you ensure that this notice is replicated 108733Sgeoffrey.blake@arm.com# unmodified and in its entirety in all distributions of the software, 118733Sgeoffrey.blake@arm.com# modified or unmodified, in source code or in binary form. 128733Sgeoffrey.blake@arm.com# 138733Sgeoffrey.blake@arm.com# Redistribution and use in source and binary forms, with or without 148733Sgeoffrey.blake@arm.com# modification, are permitted provided that the following conditions are 152330SN/A# met: redistributions of source code must retain the above copyright 162330SN/A# notice, this list of conditions and the following disclaimer; 172330SN/A# redistributions in binary form must reproduce the above copyright 182330SN/A# notice, this list of conditions and the following disclaimer in the 192330SN/A# documentation and/or other materials provided with the distribution; 202330SN/A# neither the name of the copyright holders nor the names of its 212330SN/A# contributors may be used to endorse or promote products derived from 222330SN/A# this software without specific prior written permission. 232330SN/A# 242330SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 252330SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 262330SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 272330SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 282330SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 292330SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 302330SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 312330SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 322330SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 332330SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 342330SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 352330SN/A# 362330SN/A# Authors: Andreas Sandberg 372330SN/A 382330SN/Afrom m5.params import * 392330SN/Afrom m5.proxy import * 402689Sktlim@umich.edufrom m5.util.fdthelper import * 412689Sktlim@umich.edufrom m5.SimObject import SimObject 422330SN/A 432330SN/Afrom m5.objects.Device import PioDevice, BasicPioDevice 442683Sktlim@umich.edufrom m5.objects.Platform import Platform 452683Sktlim@umich.edu 462315SN/Aclass BaseGic(PioDevice): 472972Sgblack@eecs.umich.edu type = 'BaseGic' 486658Snate@binkert.org abstract = True 492315SN/A cxx_header = "dev/arm/base_gic.hh" 502683Sktlim@umich.edu 512680SN/A # Used for DTB autogeneration 528733Sgeoffrey.blake@arm.com _state = FdtState(addr_cells=0, interrupt_cells=3) 532315SN/A 542315SN/A platform = Param.Platform(Parent.any, "Platform this device is part of.") 5513905Sgabeblack@google.com 5613905Sgabeblack@google.com gicd_iidr = Param.UInt32(0, 5713905Sgabeblack@google.com "Distributor Implementer Identification Register") 583548Sgblack@eecs.umich.edu gicd_pidr = Param.UInt32(0, 599020Sgblack@eecs.umich.edu "Peripheral Identification Register") 602330SN/A gicc_iidr = Param.UInt32(0, 612315SN/A "CPU Interface Identification Register") 622350SN/A gicv_iidr = Param.UInt32(0, 632680SN/A "VM CPU Interface Identification Register") 642680SN/A 652683Sktlim@umich.edu def interruptCells(self, int_type, int_num, int_flag): 662683Sktlim@umich.edu """ 672683Sktlim@umich.edu Interupt cells generation helper: 682683Sktlim@umich.edu Following specifications described in 692350SN/A 702680SN/A Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt 712680SN/A """ 722315SN/A assert self._state.interrupt_cells == 3 732315SN/A return [ int_type, int_num, int_flag ] 742680SN/A 752683Sktlim@umich.educlass ArmInterruptPin(SimObject): 762683Sktlim@umich.edu type = 'ArmInterruptPin' 772330SN/A cxx_header = "dev/arm/base_gic.hh" 782315SN/A cxx_class = "ArmInterruptPinGen" 792315SN/A abstract = True 802315SN/A 812683Sktlim@umich.edu platform = Param.Platform(Parent.any, "Platform with interrupt controller") 822683Sktlim@umich.edu num = Param.UInt32("Interrupt number in GIC") 832680SN/A 842683Sktlim@umich.educlass ArmSPI(ArmInterruptPin): 852683Sktlim@umich.edu type = 'ArmSPI' 862683Sktlim@umich.edu cxx_header = "dev/arm/base_gic.hh" 872683Sktlim@umich.edu cxx_class = "ArmSPIGen" 882683Sktlim@umich.edu 892315SN/Aclass ArmPPI(ArmInterruptPin): 902315SN/A type = 'ArmPPI' 912315SN/A cxx_header = "dev/arm/base_gic.hh" 922315SN/A cxx_class = "ArmPPIGen" 9313628SAndrea.Mondelli@ucf.edu 942315SN/Aclass GicV2(BaseGic): 9513628SAndrea.Mondelli@ucf.edu type = 'GicV2' 9610190Sakash.bagdia@arm.com cxx_header = "dev/arm/gic_v2.hh" 9713628SAndrea.Mondelli@ucf.edu 988733Sgeoffrey.blake@arm.com dist_addr = Param.Addr("Address for distributor") 9913628SAndrea.Mondelli@ucf.edu cpu_addr = Param.Addr("Address for cpu") 1008733Sgeoffrey.blake@arm.com cpu_size = Param.Addr(0x2000, "Size of cpu register bank") 10113865Sgabeblack@google.com dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor") 10213865Sgabeblack@google.com cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface") 1032315SN/A int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU") 1048733Sgeoffrey.blake@arm.com it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)") 1058733Sgeoffrey.blake@arm.com gem5_extensions = Param.Bool(False, "Enable gem5 extensions") 1062315SN/A 1072315SN/Aclass Gic400(GicV2): 1088733Sgeoffrey.blake@arm.com """ 10913628SAndrea.Mondelli@ucf.edu As defined in: 11013865Sgabeblack@google.com "ARM Generic Interrupt Controller Architecture" version 2.0 11113865Sgabeblack@google.com "CoreLink GIC-400 Generic Interrupt Controller" revision r0p1 1128733Sgeoffrey.blake@arm.com """ 1138733Sgeoffrey.blake@arm.com gicd_pidr = 0x002bb490 1148733Sgeoffrey.blake@arm.com gicd_iidr = 0x0200143B 1158733Sgeoffrey.blake@arm.com gicc_iidr = 0x0202143B 1162315SN/A 11713628SAndrea.Mondelli@ucf.edu # gicv_iidr same as gicc_idr 1184997Sgblack@eecs.umich.edu gicv_iidr = gicc_iidr 11913628SAndrea.Mondelli@ucf.edu 1204997Sgblack@eecs.umich.educlass Gicv2mFrame(SimObject): 12113865Sgabeblack@google.com type = 'Gicv2mFrame' 12213865Sgabeblack@google.com cxx_header = "dev/arm/gic_v2m.hh" 1238887Sgeoffrey.blake@arm.com spi_base = Param.UInt32(0x0, "Frame SPI base number"); 1248887Sgeoffrey.blake@arm.com spi_len = Param.UInt32(0x0, "Frame SPI total number"); 1258887Sgeoffrey.blake@arm.com addr = Param.Addr("Address for frame PIO") 1268733Sgeoffrey.blake@arm.com 12713693Sgiacomo.gabrielli@arm.comclass Gicv2m(PioDevice): 12813693Sgiacomo.gabrielli@arm.com type = 'Gicv2m' 12913865Sgabeblack@google.com cxx_header = "dev/arm/gic_v2m.hh" 13013865Sgabeblack@google.com 13113865Sgabeblack@google.com pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 13213628SAndrea.Mondelli@ucf.edu gic = Param.BaseGic(Parent.any, "Gic on which to trigger interrupts") 13313628SAndrea.Mondelli@ucf.edu frames = VectorParam.Gicv2mFrame([], "Power of two number of frames") 1348733Sgeoffrey.blake@arm.com 13513628SAndrea.Mondelli@ucf.educlass VGic(PioDevice): 1362315SN/A type = 'VGic' 13713905Sgabeblack@google.com cxx_header = "dev/arm/vgic.hh" 13813865Sgabeblack@google.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 13913865Sgabeblack@google.com platform = Param.Platform(Parent.any, "Platform this device is part of.") 14013865Sgabeblack@google.com vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 14113865Sgabeblack@google.com hv_addr = Param.Addr(0, "Address for hv control") 1422690Sktlim@umich.edu pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 14313628SAndrea.Mondelli@ucf.edu # The number of list registers is not currently configurable at runtime. 1447679Sgblack@eecs.umich.edu maint_int = Param.UInt32("HV maintenance interrupt number") 14513628SAndrea.Mondelli@ucf.edu 14611886Sbrandon.potter@amd.com # gicv_iidr same as gicc_idr 14713628SAndrea.Mondelli@ucf.edu gicv_iidr = Param.UInt32(Self.gic.gicc_iidr, 1482690Sktlim@umich.edu "VM CPU Interface Identification Register") 14913865Sgabeblack@google.com 15013865Sgabeblack@google.com def generateDeviceTree(self, state): 15113865Sgabeblack@google.com gic = self.gic.unproxy(self) 15213865Sgabeblack@google.com 15313865Sgabeblack@google.com node = FdtNode("interrupt-controller") 1548733Sgeoffrey.blake@arm.com node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic", 15513865Sgabeblack@google.com "arm,cortex-a9-gic"]) 15613865Sgabeblack@google.com node.append(gic._state.interruptCellsProperty()) 15713865Sgabeblack@google.com node.append(gic._state.addrCellsProperty()) 15813865Sgabeblack@google.com node.append(FdtProperty("interrupt-controller")) 15913865Sgabeblack@google.com 1608733Sgeoffrey.blake@arm.com regs = ( 16113865Sgabeblack@google.com state.addrCells(gic.dist_addr) + 16213865Sgabeblack@google.com state.sizeCells(0x1000) + 1638733Sgeoffrey.blake@arm.com state.addrCells(gic.cpu_addr) + 1648733Sgeoffrey.blake@arm.com state.sizeCells(0x1000) + 1658733Sgeoffrey.blake@arm.com state.addrCells(self.hv_addr) + 1668809Sgblack@eecs.umich.edu state.sizeCells(0x2000) + 16713865Sgabeblack@google.com state.addrCells(self.vcpu_addr) + 16813865Sgabeblack@google.com state.sizeCells(0x2000) ) 16913865Sgabeblack@google.com 17013628SAndrea.Mondelli@ucf.edu node.append(FdtPropertyWords("reg", regs)) 17113628SAndrea.Mondelli@ucf.edu node.append(FdtPropertyWords("interrupts", 1722690Sktlim@umich.edu [1, int(self.maint_int)-16, 0xf04])) 1738733Sgeoffrey.blake@arm.com 17413865Sgabeblack@google.com node.appendPhandle(gic) 17513865Sgabeblack@google.com 17613865Sgabeblack@google.com yield node 17713865Sgabeblack@google.com 17813865Sgabeblack@google.comclass Gicv3Its(BasicPioDevice): 1792315SN/A type = 'Gicv3Its' 18013628SAndrea.Mondelli@ucf.edu cxx_header = "dev/arm/gic_v3_its.hh" 1812315SN/A 18213865Sgabeblack@google.com dma = MasterPort("DMA port") 18313865Sgabeblack@google.com pio_size = Param.Unsigned(0x20000, "Gicv3Its pio size") 1842330SN/A 1852680SN/A # CIL [36] = 0: ITS supports 16-bit CollectionID 1862680SN/A # Devbits [17:13] = 0b100011: ITS supports 23 DeviceID bits 1872330SN/A # ID_bits [12:8] = 0b11111: ITS supports 31 EventID bits 1882315SN/A gits_typer = Param.UInt64(0x30023F01, "GITS_TYPER RO value") 18910407Smitch.hayenga@arm.com 19013628SAndrea.Mondelli@ucf.educlass Gicv3(BaseGic): 1912315SN/A type = 'Gicv3' 1922315SN/A cxx_header = "dev/arm/gic_v3.hh" 19313865Sgabeblack@google.com 1942315SN/A # Used for DTB autogeneration 1952315SN/A _state = FdtState(addr_cells=2, size_cells=2, interrupt_cells=3) 19613865Sgabeblack@google.com 1972315SN/A its = Param.Gicv3Its(Gicv3Its(), "GICv3 Interrupt Translation Service") 19813865Sgabeblack@google.com 1992315SN/A dist_addr = Param.Addr("Address for distributor") 20013865Sgabeblack@google.com dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor") 20113865Sgabeblack@google.com redist_addr = Param.Addr("Address for redistributors") 2022315SN/A redist_pio_delay = Param.Latency('10ns', 2032680SN/A "Delay for PIO r/w to redistributors") 2043225Sktlim@umich.edu it_lines = Param.UInt32(1020, 2052315SN/A "Number of interrupt lines supported (max = 1020)") 2062315SN/A 20713865Sgabeblack@google.com maint_int = Param.ArmInterruptPin( 20813865Sgabeblack@google.com "HV maintenance interrupt." 2098733Sgeoffrey.blake@arm.com "ARM strongly recommends that maintenance interrupts " 2108733Sgeoffrey.blake@arm.com "are configured to use INTID 25 (PPI Interrupt).") 2118733Sgeoffrey.blake@arm.com 2128733Sgeoffrey.blake@arm.com cpu_max = Param.Unsigned(256, 2132315SN/A "Maximum number of PE. This is affecting the maximum number of " 21413865Sgabeblack@google.com "redistributors") 21513865Sgabeblack@google.com 21613865Sgabeblack@google.com gicv4 = Param.Bool(True, "GICv4 extension available") 21713628SAndrea.Mondelli@ucf.edu 21813628SAndrea.Mondelli@ucf.edu def interruptCells(self, int_type, int_num, int_flag): 2192315SN/A """ 22013865Sgabeblack@google.com Interupt cells generation helper: 22113865Sgabeblack@google.com Following specifications described in 2222315SN/A 22313865Sgabeblack@google.com Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt 22413865Sgabeblack@google.com """ 2252315SN/A prop = self._state.interruptCells(0) 2262315SN/A assert len(prop) >= 3 22713865Sgabeblack@google.com prop[0] = int_type 22813865Sgabeblack@google.com prop[1] = int_num 2292315SN/A prop[2] = int_flag 2302680SN/A return prop 2312680SN/A 2322315SN/A def generateDeviceTree(self, state): 2332315SN/A node = FdtNode("interrupt-controller") 23413865Sgabeblack@google.com node.appendCompatible(["arm,gic-v3"]) 23513865Sgabeblack@google.com node.append(self._state.interruptCellsProperty()) 2362315SN/A node.append(self._state.addrCellsProperty()) 2372680SN/A node.append(self._state.sizeCellsProperty()) 2382680SN/A node.append(FdtProperty("interrupt-controller")) 2392315SN/A 2402315SN/A redist_stride = 0x40000 if self.gicv4 else 0x20000 2412315SN/A node.append(FdtPropertyWords("redistributor-stride", 2422315SN/A state.sizeCells(redist_stride))) 2432315SN/A 24413865Sgabeblack@google.com regs = ( 24513865Sgabeblack@google.com state.addrCells(self.dist_addr) + 24613865Sgabeblack@google.com state.sizeCells(0x10000) + 24713628SAndrea.Mondelli@ucf.edu state.addrCells(self.redist_addr) + 24813628SAndrea.Mondelli@ucf.edu state.sizeCells(0x2000000) ) 2492315SN/A 25013557Sgabeblack@google.com node.append(FdtPropertyWords("reg", regs)) 25113865Sgabeblack@google.com node.append(FdtPropertyWords("interrupts", 25213557Sgabeblack@google.com self.interruptCells(1, int(self.maint_int.num)-16, 0xf04))) 25313611Sgabeblack@google.com 25413557Sgabeblack@google.com node.appendPhandle(self) 2552315SN/A 25613865Sgabeblack@google.com yield node 25713865Sgabeblack@google.com