Gic.py revision 13880
112739Sandreas.sandberg@arm.com# Copyright (c) 2012-2013, 2017-2018 ARM Limited 29525SAndreas.Sandberg@ARM.com# All rights reserved. 39525SAndreas.Sandberg@ARM.com# 49525SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall 59525SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual 69525SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating 79525SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software 89525SAndreas.Sandberg@ARM.com# licensed hereunder. You may use the software subject to the license 99525SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated 109525SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software, 119525SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form. 129525SAndreas.Sandberg@ARM.com# 139525SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without 149525SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are 159525SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright 169525SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer; 179525SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright 189525SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the 199525SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution; 209525SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its 219525SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from 229525SAndreas.Sandberg@ARM.com# this software without specific prior written permission. 239525SAndreas.Sandberg@ARM.com# 249525SAndreas.Sandberg@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 259525SAndreas.Sandberg@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 269525SAndreas.Sandberg@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 279525SAndreas.Sandberg@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 289525SAndreas.Sandberg@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 299525SAndreas.Sandberg@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 309525SAndreas.Sandberg@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 319525SAndreas.Sandberg@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 329525SAndreas.Sandberg@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 339525SAndreas.Sandberg@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 349525SAndreas.Sandberg@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 359525SAndreas.Sandberg@ARM.com# 369525SAndreas.Sandberg@ARM.com# Authors: Andreas Sandberg 379525SAndreas.Sandberg@ARM.com 389525SAndreas.Sandberg@ARM.comfrom m5.params import * 399525SAndreas.Sandberg@ARM.comfrom m5.proxy import * 4013591Sciro.santilli@arm.comfrom m5.util.fdthelper import * 4110749Smatt.evans@arm.comfrom m5.SimObject import SimObject 429525SAndreas.Sandberg@ARM.com 4313665Sandreas.sandberg@arm.comfrom m5.objects.Device import PioDevice 4413665Sandreas.sandberg@arm.comfrom m5.objects.Platform import Platform 459525SAndreas.Sandberg@ARM.com 469525SAndreas.Sandberg@ARM.comclass BaseGic(PioDevice): 479525SAndreas.Sandberg@ARM.com type = 'BaseGic' 489525SAndreas.Sandberg@ARM.com abstract = True 499525SAndreas.Sandberg@ARM.com cxx_header = "dev/arm/base_gic.hh" 509525SAndreas.Sandberg@ARM.com 519525SAndreas.Sandberg@ARM.com platform = Param.Platform(Parent.any, "Platform this device is part of.") 529525SAndreas.Sandberg@ARM.com 5313505Sgiacomo.travaglini@arm.com gicd_iidr = Param.UInt32(0, 5413505Sgiacomo.travaglini@arm.com "Distributor Implementer Identification Register") 5513505Sgiacomo.travaglini@arm.com gicd_pidr = Param.UInt32(0, 5613505Sgiacomo.travaglini@arm.com "Peripheral Identification Register") 5713505Sgiacomo.travaglini@arm.com gicc_iidr = Param.UInt32(0, 5813505Sgiacomo.travaglini@arm.com "CPU Interface Identification Register") 5913505Sgiacomo.travaglini@arm.com gicv_iidr = Param.UInt32(0, 6013505Sgiacomo.travaglini@arm.com "VM CPU Interface Identification Register") 6113505Sgiacomo.travaglini@arm.com 6212739Sandreas.sandberg@arm.comclass ArmInterruptPin(SimObject): 6312739Sandreas.sandberg@arm.com type = 'ArmInterruptPin' 6412739Sandreas.sandberg@arm.com cxx_header = "dev/arm/base_gic.hh" 6512974Sgiacomo.travaglini@arm.com cxx_class = "ArmInterruptPinGen" 6612739Sandreas.sandberg@arm.com abstract = True 6712739Sandreas.sandberg@arm.com 6812739Sandreas.sandberg@arm.com platform = Param.Platform(Parent.any, "Platform with interrupt controller") 6912739Sandreas.sandberg@arm.com num = Param.UInt32("Interrupt number in GIC") 7012739Sandreas.sandberg@arm.com 7112739Sandreas.sandberg@arm.comclass ArmSPI(ArmInterruptPin): 7212739Sandreas.sandberg@arm.com type = 'ArmSPI' 7312739Sandreas.sandberg@arm.com cxx_header = "dev/arm/base_gic.hh" 7412974Sgiacomo.travaglini@arm.com cxx_class = "ArmSPIGen" 7512739Sandreas.sandberg@arm.com 7612739Sandreas.sandberg@arm.comclass ArmPPI(ArmInterruptPin): 7712739Sandreas.sandberg@arm.com type = 'ArmPPI' 7812739Sandreas.sandberg@arm.com cxx_header = "dev/arm/base_gic.hh" 7912974Sgiacomo.travaglini@arm.com cxx_class = "ArmPPIGen" 8012739Sandreas.sandberg@arm.com 8113014Sciro.santilli@arm.comclass GicV2(BaseGic): 8213014Sciro.santilli@arm.com type = 'GicV2' 8313014Sciro.santilli@arm.com cxx_header = "dev/arm/gic_v2.hh" 849525SAndreas.Sandberg@ARM.com 8513013Sciro.santilli@arm.com dist_addr = Param.Addr("Address for distributor") 8613013Sciro.santilli@arm.com cpu_addr = Param.Addr("Address for cpu") 8713013Sciro.santilli@arm.com cpu_size = Param.Addr(0x2000, "Size of cpu register bank") 889525SAndreas.Sandberg@ARM.com dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor") 899525SAndreas.Sandberg@ARM.com cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface") 909525SAndreas.Sandberg@ARM.com int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU") 919525SAndreas.Sandberg@ARM.com it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)") 9211652SCurtis.Dunham@arm.com gem5_extensions = Param.Bool(False, "Enable gem5 extensions") 9310749Smatt.evans@arm.com 9413505Sgiacomo.travaglini@arm.comclass Gic400(GicV2): 9513505Sgiacomo.travaglini@arm.com """ 9613505Sgiacomo.travaglini@arm.com As defined in: 9713505Sgiacomo.travaglini@arm.com "ARM Generic Interrupt Controller Architecture" version 2.0 9813505Sgiacomo.travaglini@arm.com "CoreLink GIC-400 Generic Interrupt Controller" revision r0p1 9913505Sgiacomo.travaglini@arm.com """ 10013505Sgiacomo.travaglini@arm.com gicd_pidr = 0x002bb490 10113505Sgiacomo.travaglini@arm.com gicd_iidr = 0x0200143B 10213505Sgiacomo.travaglini@arm.com gicc_iidr = 0x0202143B 10313505Sgiacomo.travaglini@arm.com 10413505Sgiacomo.travaglini@arm.com # gicv_iidr same as gicc_idr 10513505Sgiacomo.travaglini@arm.com gicv_iidr = gicc_iidr 10613505Sgiacomo.travaglini@arm.com 10710749Smatt.evans@arm.comclass Gicv2mFrame(SimObject): 10810749Smatt.evans@arm.com type = 'Gicv2mFrame' 10910749Smatt.evans@arm.com cxx_header = "dev/arm/gic_v2m.hh" 11010749Smatt.evans@arm.com spi_base = Param.UInt32(0x0, "Frame SPI base number"); 11110749Smatt.evans@arm.com spi_len = Param.UInt32(0x0, "Frame SPI total number"); 11210749Smatt.evans@arm.com addr = Param.Addr("Address for frame PIO") 11310749Smatt.evans@arm.com 11410749Smatt.evans@arm.comclass Gicv2m(PioDevice): 11510749Smatt.evans@arm.com type = 'Gicv2m' 11610749Smatt.evans@arm.com cxx_header = "dev/arm/gic_v2m.hh" 11710749Smatt.evans@arm.com 11810749Smatt.evans@arm.com pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 11910749Smatt.evans@arm.com gic = Param.BaseGic(Parent.any, "Gic on which to trigger interrupts") 12010749Smatt.evans@arm.com frames = VectorParam.Gicv2mFrame([], "Power of two number of frames") 12113504Sgiacomo.travaglini@arm.com 12213504Sgiacomo.travaglini@arm.comclass VGic(PioDevice): 12313504Sgiacomo.travaglini@arm.com type = 'VGic' 12413504Sgiacomo.travaglini@arm.com cxx_header = "dev/arm/vgic.hh" 12513504Sgiacomo.travaglini@arm.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 12613504Sgiacomo.travaglini@arm.com platform = Param.Platform(Parent.any, "Platform this device is part of.") 12713504Sgiacomo.travaglini@arm.com vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 12813504Sgiacomo.travaglini@arm.com hv_addr = Param.Addr(0, "Address for hv control") 12913504Sgiacomo.travaglini@arm.com pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 13013504Sgiacomo.travaglini@arm.com # The number of list registers is not currently configurable at runtime. 13113814Sgiacomo.travaglini@arm.com maint_int = Param.UInt32("HV maintenance interrupt number") 13213504Sgiacomo.travaglini@arm.com 13313505Sgiacomo.travaglini@arm.com # gicv_iidr same as gicc_idr 13413505Sgiacomo.travaglini@arm.com gicv_iidr = Param.UInt32(Self.gic.gicc_iidr, 13513505Sgiacomo.travaglini@arm.com "VM CPU Interface Identification Register") 13613505Sgiacomo.travaglini@arm.com 13713504Sgiacomo.travaglini@arm.com def generateDeviceTree(self, state): 13813504Sgiacomo.travaglini@arm.com gic = self.gic.unproxy(self) 13913504Sgiacomo.travaglini@arm.com 14013504Sgiacomo.travaglini@arm.com node = FdtNode("interrupt-controller") 14113504Sgiacomo.travaglini@arm.com node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic", 14213504Sgiacomo.travaglini@arm.com "arm,cortex-a9-gic"]) 14313504Sgiacomo.travaglini@arm.com node.append(FdtPropertyWords("#interrupt-cells", [3])) 14413504Sgiacomo.travaglini@arm.com node.append(FdtPropertyWords("#address-cells", [0])) 14513504Sgiacomo.travaglini@arm.com node.append(FdtProperty("interrupt-controller")) 14613504Sgiacomo.travaglini@arm.com 14713504Sgiacomo.travaglini@arm.com regs = ( 14813504Sgiacomo.travaglini@arm.com state.addrCells(gic.dist_addr) + 14913504Sgiacomo.travaglini@arm.com state.sizeCells(0x1000) + 15013504Sgiacomo.travaglini@arm.com state.addrCells(gic.cpu_addr) + 15113504Sgiacomo.travaglini@arm.com state.sizeCells(0x1000) + 15213504Sgiacomo.travaglini@arm.com state.addrCells(self.hv_addr) + 15313504Sgiacomo.travaglini@arm.com state.sizeCells(0x2000) + 15413504Sgiacomo.travaglini@arm.com state.addrCells(self.vcpu_addr) + 15513504Sgiacomo.travaglini@arm.com state.sizeCells(0x2000) ) 15613504Sgiacomo.travaglini@arm.com 15713504Sgiacomo.travaglini@arm.com node.append(FdtPropertyWords("reg", regs)) 15813504Sgiacomo.travaglini@arm.com node.append(FdtPropertyWords("interrupts", 15913814Sgiacomo.travaglini@arm.com [1, int(self.maint_int)-16, 0xf04])) 16013504Sgiacomo.travaglini@arm.com 16113504Sgiacomo.travaglini@arm.com node.appendPhandle(gic) 16213504Sgiacomo.travaglini@arm.com 16313504Sgiacomo.travaglini@arm.com yield node 16413531Sjairo.balart@metempsy.com 16513531Sjairo.balart@metempsy.comclass Gicv3(BaseGic): 16613531Sjairo.balart@metempsy.com type = 'Gicv3' 16713531Sjairo.balart@metempsy.com cxx_header = "dev/arm/gic_v3.hh" 16813531Sjairo.balart@metempsy.com 16913880Sgiacomo.travaglini@arm.com dist_addr = Param.Addr("Address for distributor") 17013531Sjairo.balart@metempsy.com dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor") 17113880Sgiacomo.travaglini@arm.com redist_addr = Param.Addr("Address for redistributors") 17213531Sjairo.balart@metempsy.com redist_pio_delay = Param.Latency('10ns', 17313531Sjairo.balart@metempsy.com "Delay for PIO r/w to redistributors") 17413531Sjairo.balart@metempsy.com it_lines = Param.UInt32(1020, 17513531Sjairo.balart@metempsy.com "Number of interrupt lines supported (max = 1020)") 17613826Sgiacomo.travaglini@arm.com 17713826Sgiacomo.travaglini@arm.com maint_int = Param.ArmInterruptPin( 17813826Sgiacomo.travaglini@arm.com "HV maintenance interrupt." 17913826Sgiacomo.travaglini@arm.com "ARM strongly recommends that maintenance interrupts " 18013826Sgiacomo.travaglini@arm.com "are configured to use INTID 25 (PPI Interrupt).") 18113877Sgiacomo.travaglini@arm.com 18213877Sgiacomo.travaglini@arm.com cpu_max = Param.Unsigned(256, 18313877Sgiacomo.travaglini@arm.com "Maximum number of PE. This is affecting the maximum number of " 18413877Sgiacomo.travaglini@arm.com "redistributors") 18513878Sgiacomo.travaglini@arm.com 18613878Sgiacomo.travaglini@arm.com gicv4 = Param.Bool(True, "GICv4 extension available") 187