Gic.py revision 13014
112771Sqtt2@cornell.edu# Copyright (c) 2012-2013, 2017-2018 ARM Limited 212771Sqtt2@cornell.edu# All rights reserved. 312771Sqtt2@cornell.edu# 412771Sqtt2@cornell.edu# The license below extends only to copyright in the software and shall 512771Sqtt2@cornell.edu# not be construed as granting a license to any other intellectual 612771Sqtt2@cornell.edu# property including but not limited to intellectual property relating 712771Sqtt2@cornell.edu# to a hardware implementation of the functionality of the software 812771Sqtt2@cornell.edu# licensed hereunder. You may use the software subject to the license 912771Sqtt2@cornell.edu# terms below provided that you ensure that this notice is replicated 1012771Sqtt2@cornell.edu# unmodified and in its entirety in all distributions of the software, 1112771Sqtt2@cornell.edu# modified or unmodified, in source code or in binary form. 1212771Sqtt2@cornell.edu# 1312771Sqtt2@cornell.edu# Redistribution and use in source and binary forms, with or without 1412771Sqtt2@cornell.edu# modification, are permitted provided that the following conditions are 1512771Sqtt2@cornell.edu# met: redistributions of source code must retain the above copyright 1612771Sqtt2@cornell.edu# notice, this list of conditions and the following disclaimer; 1712771Sqtt2@cornell.edu# redistributions in binary form must reproduce the above copyright 1812771Sqtt2@cornell.edu# notice, this list of conditions and the following disclaimer in the 1912771Sqtt2@cornell.edu# documentation and/or other materials provided with the distribution; 2012771Sqtt2@cornell.edu# neither the name of the copyright holders nor the names of its 2112771Sqtt2@cornell.edu# contributors may be used to endorse or promote products derived from 2212771Sqtt2@cornell.edu# this software without specific prior written permission. 2312771Sqtt2@cornell.edu# 2412771Sqtt2@cornell.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2512771Sqtt2@cornell.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2612771Sqtt2@cornell.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2712771Sqtt2@cornell.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2812771Sqtt2@cornell.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2912771Sqtt2@cornell.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3012771Sqtt2@cornell.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3112771Sqtt2@cornell.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3212771Sqtt2@cornell.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3312771Sqtt2@cornell.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3412771Sqtt2@cornell.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3512771Sqtt2@cornell.edu# 3612771Sqtt2@cornell.edu# Authors: Andreas Sandberg 3712771Sqtt2@cornell.edu 3812771Sqtt2@cornell.edufrom m5.params import * 3912771Sqtt2@cornell.edufrom m5.proxy import * 4012771Sqtt2@cornell.edufrom m5.SimObject import SimObject 4112771Sqtt2@cornell.edu 4212771Sqtt2@cornell.edufrom Device import PioDevice 4312771Sqtt2@cornell.edufrom Platform import Platform 4412771Sqtt2@cornell.edu 4512771Sqtt2@cornell.educlass BaseGic(PioDevice): 4612771Sqtt2@cornell.edu type = 'BaseGic' 4712771Sqtt2@cornell.edu abstract = True 4812771Sqtt2@cornell.edu cxx_header = "dev/arm/base_gic.hh" 4912771Sqtt2@cornell.edu 5012771Sqtt2@cornell.edu platform = Param.Platform(Parent.any, "Platform this device is part of.") 5112771Sqtt2@cornell.edu 5212771Sqtt2@cornell.educlass ArmInterruptPin(SimObject): 5312771Sqtt2@cornell.edu type = 'ArmInterruptPin' 5412771Sqtt2@cornell.edu cxx_header = "dev/arm/base_gic.hh" 5512771Sqtt2@cornell.edu cxx_class = "ArmInterruptPinGen" 5612771Sqtt2@cornell.edu abstract = True 5712771Sqtt2@cornell.edu 5812771Sqtt2@cornell.edu platform = Param.Platform(Parent.any, "Platform with interrupt controller") 5912771Sqtt2@cornell.edu num = Param.UInt32("Interrupt number in GIC") 6012771Sqtt2@cornell.edu 6112771Sqtt2@cornell.educlass ArmSPI(ArmInterruptPin): 6212771Sqtt2@cornell.edu type = 'ArmSPI' 6312771Sqtt2@cornell.edu cxx_header = "dev/arm/base_gic.hh" 6412771Sqtt2@cornell.edu cxx_class = "ArmSPIGen" 6512771Sqtt2@cornell.edu 6612771Sqtt2@cornell.educlass ArmPPI(ArmInterruptPin): 6712771Sqtt2@cornell.edu type = 'ArmPPI' 6812771Sqtt2@cornell.edu cxx_header = "dev/arm/base_gic.hh" 6912771Sqtt2@cornell.edu cxx_class = "ArmPPIGen" 7012771Sqtt2@cornell.edu 7112771Sqtt2@cornell.educlass GicV2(BaseGic): 7212771Sqtt2@cornell.edu type = 'GicV2' 7312771Sqtt2@cornell.edu cxx_header = "dev/arm/gic_v2.hh" 7412771Sqtt2@cornell.edu 7512771Sqtt2@cornell.edu dist_addr = Param.Addr("Address for distributor") 7612771Sqtt2@cornell.edu cpu_addr = Param.Addr("Address for cpu") 7712771Sqtt2@cornell.edu cpu_size = Param.Addr(0x2000, "Size of cpu register bank") 7812771Sqtt2@cornell.edu dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor") 7912771Sqtt2@cornell.edu cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface") 8012771Sqtt2@cornell.edu int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU") 8112771Sqtt2@cornell.edu it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)") 8212771Sqtt2@cornell.edu gem5_extensions = Param.Bool(False, "Enable gem5 extensions") 8312771Sqtt2@cornell.edu 8412771Sqtt2@cornell.educlass Gicv2mFrame(SimObject): 8512771Sqtt2@cornell.edu type = 'Gicv2mFrame' 8612771Sqtt2@cornell.edu cxx_header = "dev/arm/gic_v2m.hh" 8712771Sqtt2@cornell.edu spi_base = Param.UInt32(0x0, "Frame SPI base number"); 8812771Sqtt2@cornell.edu spi_len = Param.UInt32(0x0, "Frame SPI total number"); 8912771Sqtt2@cornell.edu addr = Param.Addr("Address for frame PIO") 9012771Sqtt2@cornell.edu 9112771Sqtt2@cornell.educlass Gicv2m(PioDevice): 9212771Sqtt2@cornell.edu type = 'Gicv2m' 93 cxx_header = "dev/arm/gic_v2m.hh" 94 95 pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 96 gic = Param.BaseGic(Parent.any, "Gic on which to trigger interrupts") 97 frames = VectorParam.Gicv2mFrame([], "Power of two number of frames") 98