Gic.py revision 13014
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3612771Sqtt2@cornell.edu# Authors: Andreas Sandberg
3712771Sqtt2@cornell.edu
3812771Sqtt2@cornell.edufrom m5.params import *
3912771Sqtt2@cornell.edufrom m5.proxy import *
4012771Sqtt2@cornell.edufrom m5.SimObject import SimObject
4112771Sqtt2@cornell.edu
4212771Sqtt2@cornell.edufrom Device import PioDevice
4312771Sqtt2@cornell.edufrom Platform import Platform
4412771Sqtt2@cornell.edu
4512771Sqtt2@cornell.educlass BaseGic(PioDevice):
4612771Sqtt2@cornell.edu    type = 'BaseGic'
4712771Sqtt2@cornell.edu    abstract = True
4812771Sqtt2@cornell.edu    cxx_header = "dev/arm/base_gic.hh"
4912771Sqtt2@cornell.edu
5012771Sqtt2@cornell.edu    platform = Param.Platform(Parent.any, "Platform this device is part of.")
5112771Sqtt2@cornell.edu
5212771Sqtt2@cornell.educlass ArmInterruptPin(SimObject):
5312771Sqtt2@cornell.edu    type = 'ArmInterruptPin'
5412771Sqtt2@cornell.edu    cxx_header = "dev/arm/base_gic.hh"
5512771Sqtt2@cornell.edu    cxx_class = "ArmInterruptPinGen"
5612771Sqtt2@cornell.edu    abstract = True
5712771Sqtt2@cornell.edu
5812771Sqtt2@cornell.edu    platform = Param.Platform(Parent.any, "Platform with interrupt controller")
5912771Sqtt2@cornell.edu    num = Param.UInt32("Interrupt number in GIC")
6012771Sqtt2@cornell.edu
6112771Sqtt2@cornell.educlass ArmSPI(ArmInterruptPin):
6212771Sqtt2@cornell.edu    type = 'ArmSPI'
6312771Sqtt2@cornell.edu    cxx_header = "dev/arm/base_gic.hh"
6412771Sqtt2@cornell.edu    cxx_class = "ArmSPIGen"
6512771Sqtt2@cornell.edu
6612771Sqtt2@cornell.educlass ArmPPI(ArmInterruptPin):
6712771Sqtt2@cornell.edu    type = 'ArmPPI'
6812771Sqtt2@cornell.edu    cxx_header = "dev/arm/base_gic.hh"
6912771Sqtt2@cornell.edu    cxx_class = "ArmPPIGen"
7012771Sqtt2@cornell.edu
7112771Sqtt2@cornell.educlass GicV2(BaseGic):
7212771Sqtt2@cornell.edu    type = 'GicV2'
7312771Sqtt2@cornell.edu    cxx_header = "dev/arm/gic_v2.hh"
7412771Sqtt2@cornell.edu
7512771Sqtt2@cornell.edu    dist_addr = Param.Addr("Address for distributor")
7612771Sqtt2@cornell.edu    cpu_addr = Param.Addr("Address for cpu")
7712771Sqtt2@cornell.edu    cpu_size = Param.Addr(0x2000, "Size of cpu register bank")
7812771Sqtt2@cornell.edu    dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
7912771Sqtt2@cornell.edu    cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
8012771Sqtt2@cornell.edu    int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
8112771Sqtt2@cornell.edu    it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
8212771Sqtt2@cornell.edu    gem5_extensions = Param.Bool(False, "Enable gem5 extensions")
8312771Sqtt2@cornell.edu
8412771Sqtt2@cornell.educlass Gicv2mFrame(SimObject):
8512771Sqtt2@cornell.edu    type = 'Gicv2mFrame'
8612771Sqtt2@cornell.edu    cxx_header = "dev/arm/gic_v2m.hh"
8712771Sqtt2@cornell.edu    spi_base = Param.UInt32(0x0, "Frame SPI base number");
8812771Sqtt2@cornell.edu    spi_len = Param.UInt32(0x0, "Frame SPI total number");
8912771Sqtt2@cornell.edu    addr = Param.Addr("Address for frame PIO")
9012771Sqtt2@cornell.edu
9112771Sqtt2@cornell.educlass Gicv2m(PioDevice):
9212771Sqtt2@cornell.edu    type = 'Gicv2m'
93    cxx_header = "dev/arm/gic_v2m.hh"
94
95    pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
96    gic = Param.BaseGic(Parent.any, "Gic on which to trigger interrupts")
97    frames = VectorParam.Gicv2mFrame([], "Power of two number of frames")
98