tsunamireg.h revision 769
1 2#ifndef __TSUNAMIREG_H__ 3#define __TSUNAMIREG_H__ 4 5// CChip Registers 6#define TSDEV_CC_CSR 0x00 7#define TSDEV_CC_MTR 0x01 8#define TSDEV_CC_MISC 0x02 9 10#define TSDEV_CC_AAR0 0x04 11#define TSDEV_CC_AAR1 0x05 12#define TSDEV_CC_AAR2 0x06 13#define TSDEV_CC_AAR3 0x07 14#define TSDEV_CC_DIM0 0x08 15#define TSDEV_CC_DIM1 0x09 16#define TSDEV_CC_DIR0 0x0A 17#define TSDEV_CC_DIR1 0x0B 18#define TSDEV_CC_DRIR 0x0C 19#define TSDEV_CC_PRBEN 0x0D 20#define TSDEV_CC_IIC0 0x0E 21#define TSDEV_CC_IIC1 0x0F 22#define TSDEV_CC_MPR0 0x10 23#define TSDEV_CC_MPR1 0x11 24#define TSDEV_CC_MPR2 0x12 25#define TSDEV_CC_MPR3 0x13 26 27#define TSDEV_CC_DIM2 0x18 28#define TSDEV_CC_DIM3 0x19 29#define TSDEV_CC_DIR2 0x1A 30#define TSDEV_CC_DIR3 0x1B 31#define TSDEV_CC_IIC2 0x1C 32#define TSDEV_CC_IIC3 0x1D 33 34 35// PChip Registers 36#define TSDEV_PC_WSBA0 0x00 37#define TSDEV_PC_WSBA1 0x01 38#define TSDEV_PC_WSBA2 0x02 39#define TSDEV_PC_WSBA3 0x03 40#define TSDEV_PC_WSM0 0x04 41#define TSDEV_PC_WSM1 0x05 42#define TSDEV_PC_WSM2 0x06 43#define TSDEV_PC_WSM3 0x07 44#define TSDEV_PC_TBA0 0x08 45#define TSDEV_PC_TBA1 0x09 46#define TSDEV_PC_TBA2 0x0A 47#define TSDEV_PC_TBA3 0x0B 48#define TSDEV_PC_PCTL 0x0C 49#define TSDEV_PC_PLAT 0x0D 50#define TSDEV_PC_RES 0x0E 51#define TSDEV_PC_PERROR 0x0F 52#define TSDEV_PC_PERRMASK 0x10 53#define TSDEV_PC_PERRSET 0x11 54#define TSDEV_PC_TLBIV 0x12 55#define TSDEV_PC_TLBIA 0x13 56#define TSDEV_PC_PMONCTL 0x14 57#define TSDEV_PC_PMONCNT 0x15 58 59#define TSDEV_PC_SPST 0x20 60 61 62// DChip Registers 63#define TSDEV_DC_DSC 0x20 64#define TSDEV_DC_STR 0x21 65#define TSDEV_DC_DREV 0x22 66#define TSDEV_DC_DSC2 0x23 67 68// I/O Ports 69#define TSDEV_PIC1_MASK 0x21 70#define TSDEV_PIC2_MASK 0xA1 71#define TSDEV_DMA1_RESET 0x0D 72#define TSDEV_DMA2_RESET 0xDA 73#define TSDEV_DMA1_MODE 0x0B 74#define TSDEV_DMA2_MODE 0xD6 75#define TSDEV_DMA1_MASK 0x0A 76#define TSDEV_DMA2_MASK 0xD4 77 78#endif // __TSUNAMIREG_H__ 79