tsunamireg.h revision 1290 
1/*
2 * Copyright (c) 2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __TSUNAMIREG_H__
30#define __TSUNAMIREG_H__
31
32#define ALPHA_K0SEG_BASE  ULL(0xfffffc0000000000)
33
34// CChip Registers
35#define TSDEV_CC_CSR    0x00
36#define TSDEV_CC_MTR    0x01
37#define TSDEV_CC_MISC   0x02
38
39#define TSDEV_CC_AAR0   0x04
40#define TSDEV_CC_AAR1   0x05
41#define TSDEV_CC_AAR2   0x06
42#define TSDEV_CC_AAR3   0x07
43#define TSDEV_CC_DIM0   0x08
44#define TSDEV_CC_DIM1   0x09
45#define TSDEV_CC_DIR0   0x0A
46#define TSDEV_CC_DIR1   0x0B
47#define TSDEV_CC_DRIR   0x0C
48#define TSDEV_CC_PRBEN  0x0D
49#define TSDEV_CC_IIC0   0x0E
50#define TSDEV_CC_IIC1   0x0F
51#define TSDEV_CC_MPR0   0x10
52#define TSDEV_CC_MPR1   0x11
53#define TSDEV_CC_MPR2   0x12
54#define TSDEV_CC_MPR3   0x13
55
56#define TSDEV_CC_DIM2   0x18
57#define TSDEV_CC_DIM3   0x19
58#define TSDEV_CC_DIR2   0x1A
59#define TSDEV_CC_DIR3   0x1B
60#define TSDEV_CC_IIC2   0x1C
61#define TSDEV_CC_IIC3   0x1D
62
63// BigTsunami Registers
64#define TSDEV_CC_BDIMS  0x1000000
65#define TSDEV_CC_BDIRS  0x2000000
66#define TSDEV_CC_IPIQ   0x20  //0xf01a000800
67#define TSDEV_CC_IPIR   0x21  //0xf01a000840
68#define TSDEV_CC_ITIR   0x22  //0xf01a000880
69
70
71// PChip Registers
72#define TSDEV_PC_WSBA0      0x00
73#define TSDEV_PC_WSBA1      0x01
74#define TSDEV_PC_WSBA2      0x02
75#define TSDEV_PC_WSBA3      0x03
76#define TSDEV_PC_WSM0       0x04
77#define TSDEV_PC_WSM1       0x05
78#define TSDEV_PC_WSM2       0x06
79#define TSDEV_PC_WSM3       0x07
80#define TSDEV_PC_TBA0       0x08
81#define TSDEV_PC_TBA1       0x09
82#define TSDEV_PC_TBA2       0x0A
83#define TSDEV_PC_TBA3       0x0B
84#define TSDEV_PC_PCTL       0x0C
85#define TSDEV_PC_PLAT       0x0D
86#define TSDEV_PC_RES        0x0E
87#define TSDEV_PC_PERROR     0x0F
88#define TSDEV_PC_PERRMASK   0x10
89#define TSDEV_PC_PERRSET    0x11
90#define TSDEV_PC_TLBIV      0x12
91#define TSDEV_PC_TLBIA      0x13
92#define TSDEV_PC_PMONCTL    0x14
93#define TSDEV_PC_PMONCNT    0x15
94
95#define TSDEV_PC_SPST       0x20
96
97
98// DChip Registers
99#define TSDEV_DC_DSC        0x20
100#define TSDEV_DC_STR        0x21
101#define TSDEV_DC_DREV       0x22
102#define TSDEV_DC_DSC2       0x23
103
104// I/O Ports
105#define TSDEV_PIC1_MASK     0x21
106#define TSDEV_PIC2_MASK     0xA1
107#define TSDEV_PIC1_ISR      0x20
108#define TSDEV_PIC2_ISR      0xA0
109#define TSDEV_PIC1_ACK      0x20
110#define TSDEV_PIC2_ACK      0xA0
111#define TSDEV_DMA1_RESET    0x0D
112#define TSDEV_DMA2_RESET    0xDA
113#define TSDEV_DMA1_MODE     0x0B
114#define TSDEV_DMA2_MODE     0xD6
115#define TSDEV_DMA1_MASK     0x0A
116#define TSDEV_DMA2_MASK     0xD4
117#define TSDEV_TMR_CTL       0x61
118#define TSDEV_TMR2_CTL      0x43
119#define TSDEV_TMR2_DATA     0x42
120#define TSDEV_TMR0_DATA     0x40
121
122#define TSDEV_RTC_ADDR      0x70
123#define TSDEV_RTC_DATA      0x71
124
125// RTC defines
126#define RTC_SECOND          0	// second of minute [0..59]
127#define RTC_SECOND_ALARM    1	// seconds to alarm
128#define RTC_MINUTE          2	// minute of hour [0..59]
129#define RTC_MINUTE_ALARM    3	// minutes to alarm
130#define RTC_HOUR            4	// hour of day [0..23]
131#define RTC_HOUR_ALARM      5	// hours to alarm
132#define RTC_DAY_OF_WEEK     6	// day of week [1..7]
133#define RTC_DAY_OF_MONTH    7	// day of month [1..31]
134#define RTC_MONTH           8	// month of year [1..12]
135#define RTC_YEAR            9	// year [00..99]
136#define RTC_CONTROL_REGISTERA   10	// control register A
137#define RTC_CONTROL_REGISTERB   11	// control register B
138#define RTC_CONTROL_REGISTERC   12	// control register C
139#define RTC_CONTROL_REGISTERD   13	// control register D
140#define RTC_REGNUMBER_RTC_CR1   0x6A	// control register 1
141
142#define PCHIP_PCI0_MEMORY       ULL(0x00000000000)
143#define PCHIP_PCI0_IO           ULL(0x001FC000000)
144#define TSUNAMI_UNCACHABLE_BIT  ULL(0x80000000000)
145#define TSUNAMI_PCI0_MEMORY     TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY
146#define TSUNAMI_PCI0_IO         TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO
147
148
149// UART Defines
150#define UART_IER_RDI            0x01
151#define UART_IER_THRI           0x02
152#define UART_IER_RLSI           0x04
153
154
155#define UART_LSR_TEMT   0x40
156#define UART_LSR_THRE   0x20
157#define UART_LSR_DR     0x01
158
159#define UART_MCR_LOOP   0x10
160
161#endif // __TSUNAMIREG_H__
162