tsunami_pchip.cc revision 809
1/* $Id$ */ 2 3/* @file 4 * Tsunami PChip (pci) 5 */ 6 7#include <deque> 8#include <string> 9#include <vector> 10 11#include "base/trace.hh" 12#include "cpu/exec_context.hh" 13#include "dev/console.hh" 14#include "dev/etherdev.hh" 15#include "dev/scsi_ctrl.hh" 16#include "dev/tlaser_clock.hh" 17#include "dev/tsunami_pchip.hh" 18#include "dev/tsunamireg.h" 19#include "dev/tsunami.hh" 20#include "mem/functional_mem/memory_control.hh" 21#include "sim/builder.hh" 22#include "sim/system.hh" 23 24using namespace std; 25 26TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a, 27 MemoryController *mmu) 28 : FunctionalMemory(name), addr(a), tsunami(t) 29{ 30 mmu->add_child(this, Range<Addr>(addr, addr + size)); 31 32 wsba0 = 0; 33 wsba1 = 0; 34 wsba2 = 0; 35 wsba3 = 0; 36 wsm0 = 0; 37 wsm1 = 0; 38 wsm2 = 0; 39 wsm3 = 0; 40 tba0 = 0; 41 tba1 = 0; 42 tba2 = 0; 43 tba3 = 0; 44 45 //Set back pointer in tsunami 46 tsunami->pchip = this; 47} 48 49Fault 50TsunamiPChip::read(MemReqPtr &req, uint8_t *data) 51{ 52 DPRINTF(Tsunami, "read va=%#x size=%d\n", 53 req->vaddr, req->size); 54 55 Addr daddr = (req->paddr & size) >> 6; 56// ExecContext *xc = req->xc; 57// int cpuid = xc->cpu_id; 58 59 switch (req->size) { 60 61 case sizeof(uint64_t): 62 switch(daddr) { 63 case TSDEV_PC_WSBA0: 64 *(uint64_t*)data = wsba0; 65 return No_Fault; 66 case TSDEV_PC_WSBA1: 67 *(uint64_t*)data = wsba1; 68 return No_Fault; 69 case TSDEV_PC_WSBA2: 70 *(uint64_t*)data = wsba2; 71 return No_Fault; 72 case TSDEV_PC_WSBA3: 73 *(uint64_t*)data = wsba3; 74 return No_Fault; 75 case TSDEV_PC_WSM0: 76 *(uint64_t*)data = wsm0; 77 return No_Fault; 78 case TSDEV_PC_WSM1: 79 *(uint64_t*)data = wsm1; 80 return No_Fault; 81 case TSDEV_PC_WSM2: 82 *(uint64_t*)data = wsm2; 83 return No_Fault; 84 case TSDEV_PC_WSM3: 85 *(uint64_t*)data = wsm3; 86 return No_Fault; 87 case TSDEV_PC_TBA0: 88 *(uint64_t*)data = tba0; 89 return No_Fault; 90 case TSDEV_PC_TBA1: 91 *(uint64_t*)data = tba1; 92 return No_Fault; 93 case TSDEV_PC_TBA2: 94 *(uint64_t*)data = tba2; 95 return No_Fault; 96 case TSDEV_PC_TBA3: 97 *(uint64_t*)data = tba3; 98 return No_Fault; 99 case TSDEV_PC_PCTL: 100 // might want to change the clock?? 101 *(uint64_t*)data = 0x00; // try this 102 return No_Fault; 103 case TSDEV_PC_PLAT: 104 panic("PC_PLAT not implemented\n"); 105 case TSDEV_PC_RES: 106 panic("PC_RES not implemented\n"); 107 case TSDEV_PC_PERROR: 108 panic("PC_PERROR not implemented\n"); 109 case TSDEV_PC_PERRMASK: 110 panic("PC_PERRMASK not implemented\n"); 111 case TSDEV_PC_PERRSET: 112 panic("PC_PERRSET not implemented\n"); 113 case TSDEV_PC_TLBIV: 114 panic("PC_TLBIV not implemented\n"); 115 case TSDEV_PC_TLBIA: 116 *(uint64_t*)data = 0x00; // shouldn't be readable, but linux 117 return No_Fault; 118 case TSDEV_PC_PMONCTL: 119 panic("PC_PMONCTL not implemented\n"); 120 case TSDEV_PC_PMONCNT: 121 panic("PC_PMONCTN not implemented\n"); 122 default: 123 panic("Default in PChip Read reached reading 0x%x\n", daddr); 124 125 } // uint64_t 126 127 break; 128 case sizeof(uint32_t): 129 case sizeof(uint16_t): 130 case sizeof(uint8_t): 131 default: 132 panic("invalid access size(?) for tsunami register!\n\n"); 133 } 134 DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr, req->size); 135 136 return No_Fault; 137} 138 139Fault 140TsunamiPChip::write(MemReqPtr &req, const uint8_t *data) 141{ 142 DPRINTF(Tsunami, "write - va=%#x size=%d \n", 143 req->vaddr, req->size); 144 145 Addr daddr = (req->paddr & size) >> 6; 146 147 switch (req->size) { 148 149 case sizeof(uint64_t): 150 switch(daddr) { 151 case TSDEV_PC_WSBA0: 152 wsba0 = *(uint64_t*)data; 153 return No_Fault; 154 case TSDEV_PC_WSBA1: 155 wsba1 = *(uint64_t*)data; 156 return No_Fault; 157 case TSDEV_PC_WSBA2: 158 wsba2 = *(uint64_t*)data; 159 return No_Fault; 160 case TSDEV_PC_WSBA3: 161 wsba3 = *(uint64_t*)data; 162 return No_Fault; 163 case TSDEV_PC_WSM0: 164 wsm0 = *(uint64_t*)data; 165 return No_Fault; 166 case TSDEV_PC_WSM1: 167 wsm1 = *(uint64_t*)data; 168 return No_Fault; 169 case TSDEV_PC_WSM2: 170 wsm2 = *(uint64_t*)data; 171 return No_Fault; 172 case TSDEV_PC_WSM3: 173 wsm3 = *(uint64_t*)data; 174 return No_Fault; 175 case TSDEV_PC_TBA0: 176 tba0 = *(uint64_t*)data; 177 return No_Fault; 178 case TSDEV_PC_TBA1: 179 tba1 = *(uint64_t*)data; 180 return No_Fault; 181 case TSDEV_PC_TBA2: 182 tba2 = *(uint64_t*)data; 183 return No_Fault; 184 case TSDEV_PC_TBA3: 185 tba3 = *(uint64_t*)data; 186 return No_Fault; 187 case TSDEV_PC_PCTL: 188 // might want to change the clock?? 189 //*(uint64_t*)data; // try this 190 return No_Fault; 191 case TSDEV_PC_PLAT: 192 panic("PC_PLAT not implemented\n"); 193 case TSDEV_PC_RES: 194 panic("PC_RES not implemented\n"); 195 case TSDEV_PC_PERROR: 196 panic("PC_PERROR not implemented\n"); 197 case TSDEV_PC_PERRMASK: 198 panic("PC_PERRMASK not implemented\n"); 199 case TSDEV_PC_PERRSET: 200 panic("PC_PERRSET not implemented\n"); 201 case TSDEV_PC_TLBIV: 202 panic("PC_TLBIV not implemented\n"); 203 case TSDEV_PC_TLBIA: 204 return No_Fault; // value ignored, supposted to invalidate SG TLB 205 case TSDEV_PC_PMONCTL: 206 panic("PC_PMONCTL not implemented\n"); 207 case TSDEV_PC_PMONCNT: 208 panic("PC_PMONCTN not implemented\n"); 209 default: 210 panic("Default in PChip Read reached reading 0x%x\n", daddr); 211 212 } // uint64_t 213 214 break; 215 case sizeof(uint32_t): 216 case sizeof(uint16_t): 217 case sizeof(uint8_t): 218 default: 219 panic("invalid access size(?) for tsunami register!\n\n"); 220 } 221 222 DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size); 223 224 return No_Fault; 225} 226 227void 228TsunamiPChip::serialize(std::ostream &os) 229{ 230 // code should be written 231} 232 233void 234TsunamiPChip::unserialize(Checkpoint *cp, const std::string §ion) 235{ 236 //code should be written 237} 238 239BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip) 240 241 SimObjectParam<Tsunami *> tsunami; 242 SimObjectParam<MemoryController *> mmu; 243 Param<Addr> addr; 244 245END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip) 246 247BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip) 248 249 INIT_PARAM(tsunami, "Tsunami"), 250 INIT_PARAM(mmu, "Memory Controller"), 251 INIT_PARAM(addr, "Device Address") 252 253END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip) 254 255CREATE_SIM_OBJECT(TsunamiPChip) 256{ 257 return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu); 258} 259 260REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip) 261