tsunami_pchip.cc revision 768
1/* $Id$ */ 2 3/* @file 4 * Tsunami PChip (pci) 5 */ 6 7#include <deque> 8#include <string> 9#include <vector> 10 11#include "base/trace.hh" 12#include "cpu/exec_context.hh" 13#include "dev/console.hh" 14#include "dev/etherdev.hh" 15#include "dev/scsi_ctrl.hh" 16#include "dev/tlaser_clock.hh" 17#include "dev/tsunami_pchip.hh" 18#include "dev/tsunamireg.h" 19#include "dev/tsunami.hh" 20#include "mem/functional_mem/memory_control.hh" 21#include "sim/builder.hh" 22#include "sim/system.hh" 23 24using namespace std; 25 26TsunamiPChip::TsunamiPChip(const string &name, /*Tsunami *t,*/ 27 Addr addr, Addr mask, MemoryController *mmu) 28 : MmapDevice(name, addr, mask, mmu)/*, tsunami(t) */ 29{ 30 wsba0 = 0; 31 wsba1 = 0; 32 wsba2 = 0; 33 wsba3 = 0; 34 wsm0 = 0; 35 wsm1 = 0; 36 wsm2 = 0; 37 wsm3 = 0; 38 tba0 = 0; 39 tba1 = 0; 40 tba2 = 0; 41 tba3 = 0; 42 43} 44 45Fault 46TsunamiPChip::read(MemReqPtr req, uint8_t *data) 47{ 48 DPRINTF(Tsunami, "read va=%#x size=%d\n", 49 req->vaddr, req->size); 50 51 Addr daddr = (req->paddr & addr_mask) >> 6; 52// ExecContext *xc = req->xc; 53// int cpuid = xc->cpu_id; 54 55 switch (req->size) { 56 57 case sizeof(uint64_t): 58 switch(daddr) { 59 case TSDEV_PC_WSBA0: 60 *(uint64_t*)data = wsba0; 61 return No_Fault; 62 case TSDEV_PC_WSBA1: 63 *(uint64_t*)data = wsba1; 64 return No_Fault; 65 case TSDEV_PC_WSBA2: 66 *(uint64_t*)data = wsba2; 67 return No_Fault; 68 case TSDEV_PC_WSBA3: 69 *(uint64_t*)data = wsba3; 70 return No_Fault; 71 case TSDEV_PC_WSM0: 72 *(uint64_t*)data = wsm0; 73 return No_Fault; 74 case TSDEV_PC_WSM1: 75 *(uint64_t*)data = wsm1; 76 return No_Fault; 77 case TSDEV_PC_WSM2: 78 *(uint64_t*)data = wsm2; 79 return No_Fault; 80 case TSDEV_PC_WSM3: 81 *(uint64_t*)data = wsm3; 82 return No_Fault; 83 case TSDEV_PC_TBA0: 84 *(uint64_t*)data = tba0; 85 return No_Fault; 86 case TSDEV_PC_TBA1: 87 *(uint64_t*)data = tba1; 88 return No_Fault; 89 case TSDEV_PC_TBA2: 90 *(uint64_t*)data = tba2; 91 return No_Fault; 92 case TSDEV_PC_TBA3: 93 *(uint64_t*)data = tba3; 94 return No_Fault; 95 case TSDEV_PC_PCTL: 96 // might want to change the clock?? 97 *(uint64_t*)data = 0x00; // try this 98 return No_Fault; 99 case TSDEV_PC_PLAT: 100 panic("PC_PLAT not implemented\n"); 101 case TSDEV_PC_RES: 102 panic("PC_RES not implemented\n"); 103 case TSDEV_PC_PERROR: 104 panic("PC_PERROR not implemented\n"); 105 case TSDEV_PC_PERRMASK: 106 panic("PC_PERRMASK not implemented\n"); 107 case TSDEV_PC_PERRSET: 108 panic("PC_PERRSET not implemented\n"); 109 case TSDEV_PC_TLBIV: 110 panic("PC_TLBIV not implemented\n"); 111 case TSDEV_PC_TLBIA: 112 *(uint64_t*)data = 0x00; // shouldn't be readable, but linux 113 return No_Fault; 114 case TSDEV_PC_PMONCTL: 115 panic("PC_PMONCTL not implemented\n"); 116 case TSDEV_PC_PMONCNT: 117 panic("PC_PMONCTN not implemented\n"); 118 default: 119 panic("Default in PChip Read reached reading 0x%x\n", daddr); 120 121 } // uint64_t 122 123 break; 124 case sizeof(uint32_t): 125 case sizeof(uint16_t): 126 case sizeof(uint8_t): 127 default: 128 panic("invalid access size(?) for tsunami register!\n\n"); 129 } 130 DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr, req->size); 131 132 return No_Fault; 133} 134 135Fault 136TsunamiPChip::write(MemReqPtr req, const uint8_t *data) 137{ 138 DPRINTF(Tsunami, "write - va=%#x size=%d \n", 139 req->vaddr, req->size); 140 141 Addr daddr = (req->paddr & addr_mask) >> 6; 142 143 switch (req->size) { 144 145 case sizeof(uint64_t): 146 switch(daddr) { 147 case TSDEV_PC_WSBA0: 148 wsba0 = *(uint64_t*)data; 149 return No_Fault; 150 case TSDEV_PC_WSBA1: 151 wsba1 = *(uint64_t*)data; 152 return No_Fault; 153 case TSDEV_PC_WSBA2: 154 wsba2 = *(uint64_t*)data; 155 return No_Fault; 156 case TSDEV_PC_WSBA3: 157 wsba3 = *(uint64_t*)data; 158 return No_Fault; 159 case TSDEV_PC_WSM0: 160 wsm0 = *(uint64_t*)data; 161 return No_Fault; 162 case TSDEV_PC_WSM1: 163 wsm1 = *(uint64_t*)data; 164 return No_Fault; 165 case TSDEV_PC_WSM2: 166 wsm2 = *(uint64_t*)data; 167 return No_Fault; 168 case TSDEV_PC_WSM3: 169 wsm3 = *(uint64_t*)data; 170 return No_Fault; 171 case TSDEV_PC_TBA0: 172 tba0 = *(uint64_t*)data; 173 return No_Fault; 174 case TSDEV_PC_TBA1: 175 tba1 = *(uint64_t*)data; 176 return No_Fault; 177 case TSDEV_PC_TBA2: 178 tba2 = *(uint64_t*)data; 179 return No_Fault; 180 case TSDEV_PC_TBA3: 181 tba3 = *(uint64_t*)data; 182 return No_Fault; 183 case TSDEV_PC_PCTL: 184 // might want to change the clock?? 185 //*(uint64_t*)data; // try this 186 return No_Fault; 187 case TSDEV_PC_PLAT: 188 panic("PC_PLAT not implemented\n"); 189 case TSDEV_PC_RES: 190 panic("PC_RES not implemented\n"); 191 case TSDEV_PC_PERROR: 192 panic("PC_PERROR not implemented\n"); 193 case TSDEV_PC_PERRMASK: 194 panic("PC_PERRMASK not implemented\n"); 195 case TSDEV_PC_PERRSET: 196 panic("PC_PERRSET not implemented\n"); 197 case TSDEV_PC_TLBIV: 198 panic("PC_TLBIV not implemented\n"); 199 case TSDEV_PC_TLBIA: 200 return No_Fault; // value ignored, supposted to invalidate SG TLB 201 case TSDEV_PC_PMONCTL: 202 panic("PC_PMONCTL not implemented\n"); 203 case TSDEV_PC_PMONCNT: 204 panic("PC_PMONCTN not implemented\n"); 205 default: 206 panic("Default in PChip Read reached reading 0x%x\n", daddr); 207 208 } // uint64_t 209 210 break; 211 case sizeof(uint32_t): 212 case sizeof(uint16_t): 213 case sizeof(uint8_t): 214 default: 215 panic("invalid access size(?) for tsunami register!\n\n"); 216 } 217 218 DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size); 219 220 return No_Fault; 221} 222 223void 224TsunamiPChip::serialize(std::ostream &os) 225{ 226 // code should be written 227} 228 229void 230TsunamiPChip::unserialize(Checkpoint *cp, const std::string §ion) 231{ 232 //code should be written 233} 234 235BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip) 236 237/* SimObjectParam<Tsunami *> tsunami;*/ 238 SimObjectParam<MemoryController *> mmu; 239 Param<Addr> addr; 240 Param<Addr> mask; 241 242END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip) 243 244BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip) 245 246 /*INIT_PARAM(tsunami, "Tsunami"),*/ 247 INIT_PARAM(mmu, "Memory Controller"), 248 INIT_PARAM(addr, "Device Address"), 249 INIT_PARAM(mask, "Address Mask") 250 251END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip) 252 253CREATE_SIM_OBJECT(TsunamiPChip) 254{ 255 return new TsunamiPChip(getInstanceName(), /*tsunami,*/ addr, mask, mmu); 256} 257 258REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip) 259