tsunami_pchip.cc revision 10905
1892SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 3892SN/A * All rights reserved. 4892SN/A * 5892SN/A * Redistribution and use in source and binary forms, with or without 6892SN/A * modification, are permitted provided that the following conditions are 7892SN/A * met: redistributions of source code must retain the above copyright 8892SN/A * notice, this list of conditions and the following disclaimer; 9892SN/A * redistributions in binary form must reproduce the above copyright 10892SN/A * notice, this list of conditions and the following disclaimer in the 11892SN/A * documentation and/or other materials provided with the distribution; 12892SN/A * neither the name of the copyright holders nor the names of its 13892SN/A * contributors may be used to endorse or promote products derived from 14892SN/A * this software without specific prior written permission. 15892SN/A * 16892SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17892SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18892SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19892SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20892SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21892SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22892SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23892SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24892SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25892SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26892SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Ali Saidi 292665SN/A * Andrew Schultz 30892SN/A */ 31768SN/A 321730SN/A/** @file 33768SN/A * Tsunami PChip (pci) 34768SN/A */ 35768SN/A 36768SN/A#include <deque> 37768SN/A#include <string> 38768SN/A#include <vector> 39768SN/A 40768SN/A#include "base/trace.hh" 416658Snate@binkert.org#include "config/the_isa.hh" 428232Snate@binkert.org#include "debug/Tsunami.hh" 438229Snate@binkert.org#include "dev/alpha/tsunami.hh" 443540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_pchip.hh" 453540Sgblack@eecs.umich.edu#include "dev/alpha/tsunamireg.h" 462542SN/A#include "mem/packet.hh" 473348SN/A#include "mem/packet_access.hh" 48768SN/A#include "sim/system.hh" 49768SN/A 50768SN/Ausing namespace std; 512107SN/A//Should this be AlphaISA? 522107SN/Ausing namespace TheISA; 53768SN/A 544762Snate@binkert.orgTsunamiPChip::TsunamiPChip(const Params *p) 559808Sstever@gmail.com : BasicPioDevice(p, 0x1000) 56768SN/A{ 57835SN/A for (int i = 0; i < 4; i++) { 58835SN/A wsba[i] = 0; 59835SN/A wsm[i] = 0; 60835SN/A tba[i] = 0; 61835SN/A } 62768SN/A 63896SN/A // initialize pchip control register 64896SN/A pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36); 65896SN/A 66775SN/A //Set back pointer in tsunami 672539SN/A p->tsunami->pchip = this; 682539SN/A} 692539SN/A 702539SN/ATick 713349SN/ATsunamiPChip::read(PacketPtr pkt) 722539SN/A{ 732641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 742539SN/A 752641SN/A Addr daddr = (pkt->getAddr() - pioAddr) >> 6;; 762641SN/A assert(pkt->getSize() == sizeof(uint64_t)); 772539SN/A 782539SN/A 792641SN/A DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); 802539SN/A 812539SN/A switch(daddr) { 822539SN/A case TSDEV_PC_WSBA0: 832630SN/A pkt->set(wsba[0]); 842539SN/A break; 852539SN/A case TSDEV_PC_WSBA1: 862630SN/A pkt->set(wsba[1]); 872539SN/A break; 882539SN/A case TSDEV_PC_WSBA2: 892630SN/A pkt->set(wsba[2]); 902539SN/A break; 912539SN/A case TSDEV_PC_WSBA3: 922630SN/A pkt->set(wsba[3]); 932539SN/A break; 942539SN/A case TSDEV_PC_WSM0: 952630SN/A pkt->set(wsm[0]); 962539SN/A break; 972539SN/A case TSDEV_PC_WSM1: 982630SN/A pkt->set(wsm[1]); 992539SN/A break; 1002539SN/A case TSDEV_PC_WSM2: 1012630SN/A pkt->set(wsm[2]); 1022539SN/A break; 1032539SN/A case TSDEV_PC_WSM3: 1042630SN/A pkt->set(wsm[3]); 1052539SN/A break; 1062539SN/A case TSDEV_PC_TBA0: 1072630SN/A pkt->set(tba[0]); 1082539SN/A break; 1092539SN/A case TSDEV_PC_TBA1: 1102630SN/A pkt->set(tba[1]); 1112539SN/A break; 1122539SN/A case TSDEV_PC_TBA2: 1132630SN/A pkt->set(tba[2]); 1142539SN/A break; 1152542SN/A case TSDEV_PC_TBA3: 1162630SN/A pkt->set(tba[3]); 1172539SN/A break; 1182539SN/A case TSDEV_PC_PCTL: 1192630SN/A pkt->set(pctl); 1202539SN/A break; 1212539SN/A case TSDEV_PC_PLAT: 1222539SN/A panic("PC_PLAT not implemented\n"); 1232539SN/A case TSDEV_PC_RES: 1242539SN/A panic("PC_RES not implemented\n"); 1252539SN/A case TSDEV_PC_PERROR: 1262630SN/A pkt->set((uint64_t)0x00); 1272539SN/A break; 1282539SN/A case TSDEV_PC_PERRMASK: 1292630SN/A pkt->set((uint64_t)0x00); 1302539SN/A break; 1312539SN/A case TSDEV_PC_PERRSET: 1322539SN/A panic("PC_PERRSET not implemented\n"); 1332539SN/A case TSDEV_PC_TLBIV: 1342539SN/A panic("PC_TLBIV not implemented\n"); 1352539SN/A case TSDEV_PC_TLBIA: 1362630SN/A pkt->set((uint64_t)0x00); // shouldn't be readable, but linux 1372539SN/A break; 1382539SN/A case TSDEV_PC_PMONCTL: 1392539SN/A panic("PC_PMONCTL not implemented\n"); 1402539SN/A case TSDEV_PC_PMONCNT: 1412539SN/A panic("PC_PMONCTN not implemented\n"); 1422539SN/A default: 1432539SN/A panic("Default in PChip Read reached reading 0x%x\n", daddr); 1442539SN/A } 1454870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 1462539SN/A return pioDelay; 1472539SN/A 148768SN/A} 149768SN/A 1502542SN/ATick 1513349SN/ATsunamiPChip::write(PacketPtr pkt) 152768SN/A{ 1532641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1542641SN/A Addr daddr = (pkt->getAddr() - pioAddr) >> 6; 155768SN/A 1562641SN/A assert(pkt->getSize() == sizeof(uint64_t)); 157768SN/A 1582641SN/A DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize()); 159768SN/A 1602539SN/A switch(daddr) { 1612539SN/A case TSDEV_PC_WSBA0: 1622630SN/A wsba[0] = pkt->get<uint64_t>(); 1632539SN/A break; 1642539SN/A case TSDEV_PC_WSBA1: 1652630SN/A wsba[1] = pkt->get<uint64_t>(); 1662539SN/A break; 1672539SN/A case TSDEV_PC_WSBA2: 1682630SN/A wsba[2] = pkt->get<uint64_t>(); 1692539SN/A break; 1702539SN/A case TSDEV_PC_WSBA3: 1712630SN/A wsba[3] = pkt->get<uint64_t>(); 1722539SN/A break; 1732539SN/A case TSDEV_PC_WSM0: 1742630SN/A wsm[0] = pkt->get<uint64_t>(); 1752539SN/A break; 1762539SN/A case TSDEV_PC_WSM1: 1772630SN/A wsm[1] = pkt->get<uint64_t>(); 1782539SN/A break; 1792539SN/A case TSDEV_PC_WSM2: 1802630SN/A wsm[2] = pkt->get<uint64_t>(); 1812539SN/A break; 1822539SN/A case TSDEV_PC_WSM3: 1832630SN/A wsm[3] = pkt->get<uint64_t>(); 1842539SN/A break; 1852539SN/A case TSDEV_PC_TBA0: 1862630SN/A tba[0] = pkt->get<uint64_t>(); 1872539SN/A break; 1882539SN/A case TSDEV_PC_TBA1: 1892630SN/A tba[1] = pkt->get<uint64_t>(); 1902539SN/A break; 1912539SN/A case TSDEV_PC_TBA2: 1922630SN/A tba[2] = pkt->get<uint64_t>(); 1932539SN/A break; 1942539SN/A case TSDEV_PC_TBA3: 1952630SN/A tba[3] = pkt->get<uint64_t>(); 1962539SN/A break; 1972539SN/A case TSDEV_PC_PCTL: 1982630SN/A pctl = pkt->get<uint64_t>(); 1992539SN/A break; 2002539SN/A case TSDEV_PC_PLAT: 2012539SN/A panic("PC_PLAT not implemented\n"); 2022539SN/A case TSDEV_PC_RES: 2032539SN/A panic("PC_RES not implemented\n"); 2042539SN/A case TSDEV_PC_PERROR: 2052539SN/A break; 2062539SN/A case TSDEV_PC_PERRMASK: 2072539SN/A panic("PC_PERRMASK not implemented\n"); 2082539SN/A case TSDEV_PC_PERRSET: 2092539SN/A panic("PC_PERRSET not implemented\n"); 2102539SN/A case TSDEV_PC_TLBIV: 2112539SN/A panic("PC_TLBIV not implemented\n"); 2122539SN/A case TSDEV_PC_TLBIA: 2132539SN/A break; // value ignored, supposted to invalidate SG TLB 2142539SN/A case TSDEV_PC_PMONCTL: 2152539SN/A panic("PC_PMONCTL not implemented\n"); 2162539SN/A case TSDEV_PC_PMONCNT: 2172539SN/A panic("PC_PMONCTN not implemented\n"); 2182539SN/A default: 2192549SN/A panic("Default in PChip write reached reading 0x%x\n", daddr); 220768SN/A 2212539SN/A } // uint64_t 222768SN/A 2234870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 2242539SN/A return pioDelay; 225768SN/A} 226768SN/A 227857SN/A#define DMA_ADDR_MASK ULL(0x3ffffffff) 228857SN/A 229835SN/AAddr 230835SN/ATsunamiPChip::translatePciToDma(Addr busAddr) 231835SN/A{ 232835SN/A // compare the address to the window base registers 233857SN/A uint64_t tbaMask = 0; 234857SN/A uint64_t baMask = 0; 235857SN/A 236835SN/A uint64_t windowMask = 0; 237835SN/A uint64_t windowBase = 0; 238857SN/A 239857SN/A uint64_t pteEntry = 0; 240857SN/A 241857SN/A Addr pteAddr; 242835SN/A Addr dmaAddr; 243835SN/A 244896SN/A#if 0 245896SN/A DPRINTF(IdeDisk, "Translation for bus address: %#x\n", busAddr); 246835SN/A for (int i = 0; i < 4; i++) { 247896SN/A DPRINTF(IdeDisk, "(%d) base:%#x mask:%#x\n", 248896SN/A i, wsba[i], wsm[i]); 249896SN/A 250835SN/A windowBase = wsba[i]; 251896SN/A windowMask = ~wsm[i] & (ULL(0xfff) << 20); 252835SN/A 253835SN/A if ((busAddr & windowMask) == (windowBase & windowMask)) { 254896SN/A DPRINTF(IdeDisk, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n", 255896SN/A i, windowBase, windowMask, (busAddr & windowMask), 256896SN/A (windowBase & windowMask)); 257896SN/A } 258896SN/A } 259896SN/A#endif 260857SN/A 261896SN/A for (int i = 0; i < 4; i++) { 262896SN/A 263896SN/A windowBase = wsba[i]; 264896SN/A windowMask = ~wsm[i] & (ULL(0xfff) << 20); 265896SN/A 266896SN/A if ((busAddr & windowMask) == (windowBase & windowMask)) { 267835SN/A 268835SN/A if (wsba[i] & 0x1) { // see if enabled 269857SN/A if (wsba[i] & 0x2) { // see if SG bit is set 270857SN/A /** @todo 271857SN/A This currently is faked by just doing a direct 272857SN/A read from memory, however, to be realistic, this 273857SN/A needs to actually do a bus transaction. The process 274857SN/A is explained in the tsunami documentation on page 275857SN/A 10-12 and basically munges the address to look up a 276857SN/A PTE from a table in memory and then uses that mapping 277857SN/A to create an address for the SG page 278857SN/A */ 279835SN/A 280896SN/A tbaMask = ~(((wsm[i] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff)); 281896SN/A baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13); 282857SN/A pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10); 283857SN/A 2848853Sandreas.hansson@arm.com sys->physProxy.readBlob(pteAddr, (uint8_t*)&pteEntry, 2858853Sandreas.hansson@arm.com sizeof(uint64_t)); 286857SN/A 287896SN/A dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff)); 288857SN/A 289857SN/A } else { 290896SN/A baMask = (wsm[i] & (ULL(0xfff) << 20)) | ULL(0xfffff); 291857SN/A tbaMask = ~baMask; 292857SN/A dmaAddr = (tba[i] & tbaMask) | (busAddr & baMask); 293857SN/A } 294857SN/A 295857SN/A return (dmaAddr & DMA_ADDR_MASK); 296835SN/A } 297835SN/A } 298835SN/A } 299835SN/A 300896SN/A // if no match was found, then return the original address 301896SN/A return busAddr; 302835SN/A} 3035834Sgblack@eecs.umich.edu 3042846SN/AAddr 3052846SN/ATsunamiPChip::calcConfigAddr(int bus, int dev, int func) 3062846SN/A{ 3072846SN/A assert(func < 8); 3082846SN/A assert(dev < 32); 3092846SN/A assert(bus == 0); 3102846SN/A 3112846SN/A return TsunamiPciBus0Config | (func << 8) | (dev << 11); 3122846SN/A} 3132846SN/A 3145834Sgblack@eecs.umich.eduAddr 3155834Sgblack@eecs.umich.eduTsunamiPChip::calcIOAddr(Addr addr) 3165834Sgblack@eecs.umich.edu{ 3175834Sgblack@eecs.umich.edu return TSUNAMI_PCI0_IO + addr; 3185834Sgblack@eecs.umich.edu} 3192846SN/A 3205834Sgblack@eecs.umich.eduAddr 3215834Sgblack@eecs.umich.eduTsunamiPChip::calcMemAddr(Addr addr) 3225834Sgblack@eecs.umich.edu{ 3235834Sgblack@eecs.umich.edu return TSUNAMI_PCI0_MEMORY + addr; 3245834Sgblack@eecs.umich.edu} 325835SN/A 326768SN/Avoid 32710905Sandreas.sandberg@arm.comTsunamiPChip::serialize(CheckpointOut &cp) const 328768SN/A{ 329896SN/A SERIALIZE_SCALAR(pctl); 330835SN/A SERIALIZE_ARRAY(wsba, 4); 331835SN/A SERIALIZE_ARRAY(wsm, 4); 332835SN/A SERIALIZE_ARRAY(tba, 4); 333768SN/A} 334768SN/A 335768SN/Avoid 33610905Sandreas.sandberg@arm.comTsunamiPChip::unserialize(CheckpointIn &cp) 337768SN/A{ 338896SN/A UNSERIALIZE_SCALAR(pctl); 339835SN/A UNSERIALIZE_ARRAY(wsba, 4); 340835SN/A UNSERIALIZE_ARRAY(wsm, 4); 341835SN/A UNSERIALIZE_ARRAY(tba, 4); 342768SN/A} 343768SN/A 344909SN/A 3454762Snate@binkert.orgTsunamiPChip * 3464762Snate@binkert.orgTsunamiPChipParams::create() 347768SN/A{ 3484762Snate@binkert.org return new TsunamiPChip(this); 349768SN/A} 350