tsunami_io.hh revision 5392
1768SN/A/*
21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
3768SN/A * All rights reserved.
4768SN/A *
5768SN/A * Redistribution and use in source and binary forms, with or without
6768SN/A * modification, are permitted provided that the following conditions are
7768SN/A * met: redistributions of source code must retain the above copyright
8768SN/A * notice, this list of conditions and the following disclaimer;
9768SN/A * redistributions in binary form must reproduce the above copyright
10768SN/A * notice, this list of conditions and the following disclaimer in the
11768SN/A * documentation and/or other materials provided with the distribution;
12768SN/A * neither the name of the copyright holders nor the names of its
13768SN/A * contributors may be used to endorse or promote products derived from
14768SN/A * this software without specific prior written permission.
15768SN/A *
16768SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17768SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18768SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19768SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20768SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21768SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22768SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23768SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24768SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25768SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26768SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Ali Saidi
292665SN/A *          Andrew Schultz
302665SN/A *          Miguel Serrano
31768SN/A */
32768SN/A
331722SN/A/** @file
341722SN/A * Tsunami I/O Space mapping including RTC/timer interrupts
35768SN/A */
36768SN/A
371401SN/A#ifndef __DEV_TSUNAMI_IO_HH__
381401SN/A#define __DEV_TSUNAMI_IO_HH__
39768SN/A
40909SN/A#include "base/range.hh"
413540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami.hh"
425392Sgblack@eecs.umich.edu#include "dev/mc146818.hh"
434762Snate@binkert.org#include "dev/io_device.hh"
444762Snate@binkert.org#include "params/TsunamiIO.hh"
45932SN/A#include "sim/eventq.hh"
46768SN/A
471722SN/A/**
48885SN/A * Tsunami I/O device is a catch all for all the south bridge stuff we care
49885SN/A * to implement.
50768SN/A */
512542SN/Aclass TsunamiIO : public BasicPioDevice
52768SN/A{
53809SN/A  private:
54773SN/A    struct tm tm;
55773SN/A
56768SN/A  protected:
575392Sgblack@eecs.umich.edu
585392Sgblack@eecs.umich.edu    class TsunamiRTC : public MC146818
591854SN/A    {
605392Sgblack@eecs.umich.edu      public:
615392Sgblack@eecs.umich.edu        Tsunami * tsunami;
625392Sgblack@eecs.umich.edu        TsunamiRTC(const std::string &n, const TsunamiIOParams *p);
635392Sgblack@eecs.umich.edu
645392Sgblack@eecs.umich.edu      protected:
655392Sgblack@eecs.umich.edu        void handleEvent()
661854SN/A        {
675392Sgblack@eecs.umich.edu            //Actually interrupt the processor here
685392Sgblack@eecs.umich.edu            tsunami->cchip->postRTC();
695392Sgblack@eecs.umich.edu        }
701817SN/A    };
71771SN/A
721817SN/A    /** Programmable Interval Timer (Intel 8254) */
731854SN/A    class PITimer
74772SN/A    {
751817SN/A        /** Counter element for PIT */
761854SN/A        class Counter
771817SN/A        {
781817SN/A            /** Event for counter interrupt */
791817SN/A            class CounterEvent : public Event
801817SN/A            {
811817SN/A              private:
821817SN/A                /** Pointer back to Counter */
831817SN/A                Counter* counter;
841817SN/A                Tick interval;
851817SN/A
861817SN/A              public:
871817SN/A                CounterEvent(Counter*);
881817SN/A
891817SN/A                /** Event process */
901817SN/A                virtual void process();
911817SN/A
921817SN/A                /** Event description */
935336Shines@cs.fsu.edu                virtual const char *description() const;
941817SN/A
951817SN/A                friend class Counter;
961817SN/A            };
971817SN/A
981817SN/A          private:
991854SN/A            std::string _name;
1001854SN/A            const std::string &name() const { return _name; }
1011854SN/A
1021817SN/A            CounterEvent event;
1031817SN/A
1041817SN/A            /** Current count value */
1051817SN/A            uint16_t count;
1061817SN/A
1071817SN/A            /** Latched count */
1081817SN/A            uint16_t latched_count;
1091817SN/A
1101817SN/A            /** Interrupt period */
1111817SN/A            uint16_t period;
1121817SN/A
1131817SN/A            /** Current mode of operation */
1141817SN/A            uint8_t mode;
1151817SN/A
1161817SN/A            /** Output goes high when the counter reaches zero */
1171817SN/A            bool output_high;
1181817SN/A
1191817SN/A            /** State of the count latch */
1201817SN/A            bool latch_on;
1211817SN/A
1221817SN/A            /** Set of values for read_byte and write_byte */
1231817SN/A            enum {LSB, MSB};
1241817SN/A
1251817SN/A            /** Determine which byte of a 16-bit count value to read/write */
1261817SN/A            uint8_t read_byte, write_byte;
1271817SN/A
1281817SN/A          public:
1291854SN/A            Counter(const std::string &name);
1301817SN/A
1311817SN/A            /** Latch the current count (if one is not already latched) */
1321817SN/A            void latchCount();
1331817SN/A
1341817SN/A            /** Set the read/write mode */
1351817SN/A            void setRW(int rw_val);
1361817SN/A
1371817SN/A            /** Set operational mode */
1381817SN/A            void setMode(int mode_val);
1391817SN/A
1401817SN/A            /** Set count encoding */
1411817SN/A            void setBCD(int bcd_val);
1421817SN/A
1431817SN/A            /** Read a count byte */
1442648SN/A            uint8_t read();
1451817SN/A
1461817SN/A            /** Write a count byte */
1472539SN/A            void write(const uint8_t data);
1481817SN/A
1491817SN/A            /** Is the output high? */
1501817SN/A            bool outputHigh();
1511817SN/A
1521817SN/A            /**
1531817SN/A             * Serialize this object to the given output stream.
1542982SN/A             * @param base The base name of the counter object.
1552982SN/A             * @param os   The stream to serialize to.
1561817SN/A             */
1571854SN/A            void serialize(const std::string &base, std::ostream &os);
1581817SN/A
1591817SN/A            /**
1601817SN/A             * Reconstruct the state of this object from a checkpoint.
1612982SN/A             * @param base The base name of the counter object.
1621817SN/A             * @param cp The checkpoint use.
1631817SN/A             * @param section The section name of this object
1641817SN/A             */
1651854SN/A            void unserialize(const std::string &base, Checkpoint *cp,
1661854SN/A                             const std::string &section);
1671817SN/A        };
1681817SN/A
1691817SN/A      private:
1701854SN/A        std::string _name;
1711854SN/A        const std::string &name() const { return _name; }
1721854SN/A
1731817SN/A        /** PIT has three seperate counters */
1741854SN/A        Counter *counter[3];
1751634SN/A
176772SN/A      public:
1771817SN/A        /** Public way to access individual counters (avoid array accesses) */
1781854SN/A        Counter counter0;
1791854SN/A        Counter counter1;
1801854SN/A        Counter counter2;
181772SN/A
1821854SN/A        PITimer(const std::string &name);
183885SN/A
1841817SN/A        /** Write control word */
1852539SN/A        void writeControl(const uint8_t data);
186909SN/A
1871401SN/A        /**
1881401SN/A         * Serialize this object to the given output stream.
1892982SN/A         * @param base The base name of the counter object.
1901401SN/A         * @param os The stream to serialize to.
1911401SN/A         */
1921854SN/A        void serialize(const std::string &base, std::ostream &os);
193918SN/A
1941401SN/A        /**
1951401SN/A         * Reconstruct the state of this object from a checkpoint.
1962982SN/A         * @param base The base name of the counter object.
1971401SN/A         * @param cp The checkpoint use.
1981401SN/A         * @param section The section name of this object
1991401SN/A         */
2001854SN/A        void unserialize(const std::string &base, Checkpoint *cp,
2011854SN/A                         const std::string &section);
2021401SN/A    };
203771SN/A
204885SN/A    /** Mask of the PIC1 */
205803SN/A    uint8_t mask1;
206885SN/A
207885SN/A    /** Mask of the PIC2 */
208803SN/A    uint8_t mask2;
209885SN/A
210885SN/A    /** Mode of PIC1. Not used for anything */
211803SN/A    uint8_t mode1;
212885SN/A
213885SN/A    /** Mode of PIC2. Not used for anything */
214803SN/A    uint8_t mode2;
215769SN/A
216885SN/A    /** Raw PIC interrupt register before masking */
217885SN/A    uint8_t picr; //Raw PIC interrput register
218885SN/A
219885SN/A    /** Is the pic interrupting right now or not. */
220777SN/A    bool picInterrupting;
221777SN/A
222885SN/A    /** A pointer to the Tsunami device which be belong to */
223775SN/A    Tsunami *tsunami;
224775SN/A
2251817SN/A    /** Intel 8253 Periodic Interval Timer */
2261817SN/A    PITimer pitimer;
227773SN/A
2285392Sgblack@eecs.umich.edu    TsunamiRTC rtc;
2295392Sgblack@eecs.umich.edu
2305392Sgblack@eecs.umich.edu    uint8_t rtcAddr;
231773SN/A
232885SN/A    /** The interval is set via two writes to the PIT.
233885SN/A     * This variable contains a flag as to how many writes have happened, and
234885SN/A     * the time so far.
235885SN/A     */
2361817SN/A    uint16_t timerData;
237771SN/A
238768SN/A  public:
239891SN/A    /**
240891SN/A     * Return the freqency of the RTC
241891SN/A     * @return interrupt rate of the RTC
242891SN/A     */
2431634SN/A    Tick frequency() const;
244775SN/A
2452539SN/A  public:
2464762Snate@binkert.org    typedef TsunamiIOParams Params;
247885SN/A    /**
248885SN/A     * Initialize all the data for devices supported by Tsunami I/O.
2492539SN/A     * @param p pointer to Params struct
250885SN/A     */
2514762Snate@binkert.org    TsunamiIO(const Params *p);
2524762Snate@binkert.org
2534762Snate@binkert.org    const Params *
2544762Snate@binkert.org    params() const
2554762Snate@binkert.org    {
2564762Snate@binkert.org        return dynamic_cast<const Params *>(_params);
2574762Snate@binkert.org    }
258768SN/A
2593349SN/A    virtual Tick read(PacketPtr pkt);
2603349SN/A    virtual Tick write(PacketPtr pkt);
261768SN/A
262885SN/A    /**
263885SN/A     * Post an PIC interrupt to the CPU via the CChip
264885SN/A     * @param bitvector interrupt to post.
265885SN/A     */
266777SN/A    void postPIC(uint8_t bitvector);
267885SN/A
268885SN/A    /**
269885SN/A     * Clear a posted interrupt
270885SN/A     * @param bitvector interrupt to clear
271885SN/A     */
272777SN/A    void clearPIC(uint8_t bitvector);
273777SN/A
274885SN/A    /**
275885SN/A     * Serialize this object to the given output stream.
276885SN/A     * @param os The stream to serialize to.
277885SN/A     */
278768SN/A    virtual void serialize(std::ostream &os);
279885SN/A
280885SN/A    /**
281885SN/A     * Reconstruct the state of this object from a checkpoint.
282885SN/A     * @param cp The checkpoint use.
283885SN/A     * @param section The section name of this object
284885SN/A     */
285768SN/A    virtual void unserialize(Checkpoint *cp, const std::string &section);
286909SN/A
287768SN/A};
288768SN/A
2891401SN/A#endif // __DEV_TSUNAMI_IO_HH__
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