tsunami_io.hh revision 1854 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file
30 * Tsunami I/O Space mapping including RTC/timer interrupts
31 */
32
33#ifndef __DEV_TSUNAMI_IO_HH__
34#define __DEV_TSUNAMI_IO_HH__
35
36#include "dev/io_device.hh"
37#include "base/range.hh"
38#include "dev/tsunami.hh"
39#include "sim/eventq.hh"
40
41/**
42 * Tsunami I/O device is a catch all for all the south bridge stuff we care
43 * to implement.
44 */
45class TsunamiIO : public PioDevice
46{
47  private:
48    /** The base address of this device */
49    Addr addr;
50
51    /** The size of mappad from the above address */
52    static const Addr size = 0xff;
53
54    struct tm tm;
55
56  protected:
57    /** Real-Time Clock (MC146818) */
58    class RTC
59    {
60      private:
61        /** Event for RTC periodic interrupt */
62        struct RTCEvent : public Event
63        {
64            /** A pointer back to tsunami to create interrupt the processor. */
65            Tsunami* tsunami;
66            Tick interval;
67
68            RTCEvent(Tsunami* t, Tick i);
69
70            /** Schedule the RTC periodic interrupt */
71            void scheduleIntr();
72
73            /** Event process to occur at interrupt*/
74            virtual void process();
75
76            /** Event description */
77            virtual const char *description();
78        };
79
80      private:
81        std::string _name;
82        const std::string &name() const { return _name; }
83
84        /** RTC periodic interrupt event */
85        RTCEvent event;
86
87        /** Current RTC register address/index */
88        int addr;
89
90        /** Data for real-time clock function */
91        union {
92            uint8_t clock_data[10];
93
94            struct {
95                uint8_t sec;
96                uint8_t sec_alrm;
97                uint8_t min;
98                uint8_t min_alrm;
99                uint8_t hour;
100                uint8_t hour_alrm;
101                uint8_t wday;
102                uint8_t mday;
103                uint8_t mon;
104                uint8_t year;
105            };
106        };
107
108        /** RTC status register A */
109        uint8_t stat_regA;
110
111        /** RTC status register B */
112        uint8_t stat_regB;
113
114      public:
115        RTC(const std::string &name, Tsunami* t, Tick i);
116
117        /** Set the initial RTC time/date */
118        void set_time(time_t t);
119
120        /** RTC address port: write address of RTC RAM data to access */
121        void writeAddr(const uint8_t *data);
122
123        /** RTC write data */
124        void writeData(const uint8_t *data);
125
126        /** RTC read data */
127        void readData(uint8_t *data);
128
129        /**
130          * Serialize this object to the given output stream.
131          * @param os The stream to serialize to.
132          */
133        void serialize(const std::string &base, std::ostream &os);
134
135        /**
136         * Reconstruct the state of this object from a checkpoint.
137         * @param cp The checkpoint use.
138         * @param section The section name of this object
139         */
140        void unserialize(const std::string &base, Checkpoint *cp,
141                         const std::string &section);
142    };
143
144    /** Programmable Interval Timer (Intel 8254) */
145    class PITimer
146    {
147        /** Counter element for PIT */
148        class Counter
149        {
150            /** Event for counter interrupt */
151            class CounterEvent : public Event
152            {
153              private:
154                /** Pointer back to Counter */
155                Counter* counter;
156                Tick interval;
157
158              public:
159                CounterEvent(Counter*);
160
161                /** Event process */
162                virtual void process();
163
164                /** Event description */
165                virtual const char *description();
166
167                friend class Counter;
168            };
169
170          private:
171            std::string _name;
172            const std::string &name() const { return _name; }
173
174            CounterEvent event;
175
176            /** Current count value */
177            uint16_t count;
178
179            /** Latched count */
180            uint16_t latched_count;
181
182            /** Interrupt period */
183            uint16_t period;
184
185            /** Current mode of operation */
186            uint8_t mode;
187
188            /** Output goes high when the counter reaches zero */
189            bool output_high;
190
191            /** State of the count latch */
192            bool latch_on;
193
194            /** Set of values for read_byte and write_byte */
195            enum {LSB, MSB};
196
197            /** Determine which byte of a 16-bit count value to read/write */
198            uint8_t read_byte, write_byte;
199
200          public:
201            Counter(const std::string &name);
202
203            /** Latch the current count (if one is not already latched) */
204            void latchCount();
205
206            /** Set the read/write mode */
207            void setRW(int rw_val);
208
209            /** Set operational mode */
210            void setMode(int mode_val);
211
212            /** Set count encoding */
213            void setBCD(int bcd_val);
214
215            /** Read a count byte */
216            void read(uint8_t *data);
217
218            /** Write a count byte */
219            void write(const uint8_t *data);
220
221            /** Is the output high? */
222            bool outputHigh();
223
224            /**
225             * Serialize this object to the given output stream.
226             * @param os The stream to serialize to.
227             */
228            void serialize(const std::string &base, std::ostream &os);
229
230            /**
231             * Reconstruct the state of this object from a checkpoint.
232             * @param cp The checkpoint use.
233             * @param section The section name of this object
234             */
235            void unserialize(const std::string &base, Checkpoint *cp,
236                             const std::string &section);
237        };
238
239      private:
240        std::string _name;
241        const std::string &name() const { return _name; }
242
243        /** PIT has three seperate counters */
244        Counter *counter[3];
245
246      public:
247        /** Public way to access individual counters (avoid array accesses) */
248        Counter counter0;
249        Counter counter1;
250        Counter counter2;
251
252        PITimer(const std::string &name);
253
254        /** Write control word */
255        void writeControl(const uint8_t* data);
256
257        /**
258         * Serialize this object to the given output stream.
259         * @param os The stream to serialize to.
260         */
261        void serialize(const std::string &base, std::ostream &os);
262
263        /**
264         * Reconstruct the state of this object from a checkpoint.
265         * @param cp The checkpoint use.
266         * @param section The section name of this object
267         */
268        void unserialize(const std::string &base, Checkpoint *cp,
269                         const std::string &section);
270    };
271
272    /** Mask of the PIC1 */
273    uint8_t mask1;
274
275    /** Mask of the PIC2 */
276    uint8_t mask2;
277
278    /** Mode of PIC1. Not used for anything */
279    uint8_t mode1;
280
281    /** Mode of PIC2. Not used for anything */
282    uint8_t mode2;
283
284    /** Raw PIC interrupt register before masking */
285    uint8_t picr; //Raw PIC interrput register
286
287    /** Is the pic interrupting right now or not. */
288    bool picInterrupting;
289
290    Tick clockInterval;
291
292    /** A pointer to the Tsunami device which be belong to */
293    Tsunami *tsunami;
294
295    /** Intel 8253 Periodic Interval Timer */
296    PITimer pitimer;
297
298    RTC rtc;
299
300    /** The interval is set via two writes to the PIT.
301     * This variable contains a flag as to how many writes have happened, and
302     * the time so far.
303     */
304    uint16_t timerData;
305
306  public:
307    /**
308     * Return the freqency of the RTC
309     * @return interrupt rate of the RTC
310     */
311    Tick frequency() const;
312
313    /**
314     * Initialize all the data for devices supported by Tsunami I/O.
315     * @param name name of this device.
316     * @param t pointer back to the Tsunami object that we belong to.
317     * @param init_time Time (as in seconds since 1970) to set RTC to.
318     * @param a address we are mapped at.
319     * @param mmu pointer to the memory controller that sends us events.
320     */
321    TsunamiIO(const std::string &name, Tsunami *t, time_t init_time,
322              Addr a, MemoryController *mmu, HierParams *hier, Bus *bus,
323              Tick pio_latency, Tick ci);
324
325    /**
326      * Process a read to one of the devices we are emulating.
327      * @param req Contains the address to read from.
328      * @param data A pointer to write the read data to.
329      * @return The fault condition of the access.
330      */
331    virtual Fault read(MemReqPtr &req, uint8_t *data);
332
333    /**
334      * Process a write to one of the devices we emulate.
335      * @param req Contains the address to write to.
336      * @param data The data to write.
337      * @return The fault condition of the access.
338      */
339    virtual Fault write(MemReqPtr &req, const uint8_t *data);
340
341    /**
342     * Post an PIC interrupt to the CPU via the CChip
343     * @param bitvector interrupt to post.
344     */
345    void postPIC(uint8_t bitvector);
346
347    /**
348     * Clear a posted interrupt
349     * @param bitvector interrupt to clear
350     */
351    void clearPIC(uint8_t bitvector);
352
353    /**
354     * Serialize this object to the given output stream.
355     * @param os The stream to serialize to.
356     */
357    virtual void serialize(std::ostream &os);
358
359    /**
360     * Reconstruct the state of this object from a checkpoint.
361     * @param cp The checkpoint use.
362     * @param section The section name of this object
363     */
364    virtual void unserialize(Checkpoint *cp, const std::string &section);
365
366    Tick cacheAccess(MemReqPtr &req);
367};
368
369#endif // __DEV_TSUNAMI_IO_HH__
370