tsunami_io.cc revision 8737:770ccf3af571 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 *          Andrew Schultz
30 *          Miguel Serrano
31 */
32
33/** @file
34 * Tsunami I/O including PIC, PIT, RTC, DMA
35 */
36
37#include <sys/time.h>
38
39#include <deque>
40#include <string>
41#include <vector>
42
43#include "base/time.hh"
44#include "base/trace.hh"
45#include "config/the_isa.hh"
46#include "debug/Tsunami.hh"
47#include "dev/alpha/tsunami.hh"
48#include "dev/alpha/tsunami_cchip.hh"
49#include "dev/alpha/tsunami_io.hh"
50#include "dev/alpha/tsunamireg.h"
51#include "dev/rtcreg.h"
52#include "mem/packet.hh"
53#include "mem/packet_access.hh"
54#include "mem/port.hh"
55#include "sim/system.hh"
56
57// clang complains about std::set being overloaded with Packet::set if
58// we open up the entire namespace std
59using std::string;
60using std::ostream;
61
62//Should this be AlphaISA?
63using namespace TheISA;
64
65TsunamiIO::RTC::RTC(const string &n, const TsunamiIOParams *p)
66    : MC146818(p->tsunami, n, p->time, p->year_is_bcd, p->frequency),
67      tsunami(p->tsunami)
68{
69}
70
71TsunamiIO::TsunamiIO(const Params *p)
72    : BasicPioDevice(p), tsunami(p->tsunami),
73      pitimer(this, p->name + "pitimer"), rtc(p->name + ".rtc", p)
74{
75    pioSize = 0x100;
76
77    // set the back pointer from tsunami to myself
78    tsunami->io = this;
79
80    timerData = 0;
81    picr = 0;
82    picInterrupting = false;
83}
84
85Tick
86TsunamiIO::frequency() const
87{
88    return SimClock::Frequency / params()->frequency;
89}
90
91Tick
92TsunamiIO::read(PacketPtr pkt)
93{
94    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
95
96    Addr daddr = pkt->getAddr() - pioAddr;
97
98    DPRINTF(Tsunami, "io read  va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(),
99            pkt->getSize(), daddr);
100
101    pkt->allocate();
102
103    if (pkt->getSize() == sizeof(uint8_t)) {
104        switch(daddr) {
105          // PIC1 mask read
106          case TSDEV_PIC1_MASK:
107            pkt->set(~mask1);
108            break;
109          case TSDEV_PIC2_MASK:
110            pkt->set(~mask2);
111            break;
112          case TSDEV_PIC1_ISR:
113              // !!! If this is modified 64bit case needs to be too
114              // Pal code has to do a 64 bit physical read because there is
115              // no load physical byte instruction
116              pkt->set(picr);
117              break;
118          case TSDEV_PIC2_ISR:
119              // PIC2 not implemnted... just return 0
120              pkt->set(0x00);
121              break;
122          case TSDEV_TMR0_DATA:
123            pkt->set(pitimer.readCounter(0));
124            break;
125          case TSDEV_TMR1_DATA:
126            pkt->set(pitimer.readCounter(1));
127            break;
128          case TSDEV_TMR2_DATA:
129            pkt->set(pitimer.readCounter(2));
130            break;
131          case TSDEV_RTC_DATA:
132            pkt->set(rtc.readData(rtcAddr));
133            break;
134          case TSDEV_CTRL_PORTB:
135            if (pitimer.outputHigh(2))
136                pkt->set(PORTB_SPKR_HIGH);
137            else
138                pkt->set(0x00);
139            break;
140          default:
141            panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize());
142        }
143    } else if (pkt->getSize() == sizeof(uint64_t)) {
144        if (daddr == TSDEV_PIC1_ISR)
145            pkt->set<uint64_t>(picr);
146        else
147           panic("I/O Read - invalid addr - va %#x size %d\n",
148                   pkt->getAddr(), pkt->getSize());
149    } else {
150       panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize());
151    }
152    pkt->makeAtomicResponse();
153    return pioDelay;
154}
155
156Tick
157TsunamiIO::write(PacketPtr pkt)
158{
159    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
160    Addr daddr = pkt->getAddr() - pioAddr;
161
162    DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
163            pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff, (uint32_t)pkt->get<uint8_t>());
164
165    assert(pkt->getSize() == sizeof(uint8_t));
166
167    switch(daddr) {
168      case TSDEV_PIC1_MASK:
169        mask1 = ~(pkt->get<uint8_t>());
170        if ((picr & mask1) && !picInterrupting) {
171            picInterrupting = true;
172            tsunami->cchip->postDRIR(55);
173            DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
174        }
175        if ((!(picr & mask1)) && picInterrupting) {
176            picInterrupting = false;
177            tsunami->cchip->clearDRIR(55);
178            DPRINTF(Tsunami, "clearing pic interrupt\n");
179        }
180        break;
181      case TSDEV_PIC2_MASK:
182        mask2 = pkt->get<uint8_t>();
183        //PIC2 Not implemented to interrupt
184        break;
185      case TSDEV_PIC1_ACK:
186        // clear the interrupt on the PIC
187        picr &= ~(1 << (pkt->get<uint8_t>() & 0xF));
188        if (!(picr & mask1))
189            tsunami->cchip->clearDRIR(55);
190        break;
191      case TSDEV_DMA1_MODE:
192        mode1 = pkt->get<uint8_t>();
193        break;
194      case TSDEV_DMA2_MODE:
195        mode2 = pkt->get<uint8_t>();
196        break;
197      case TSDEV_TMR0_DATA:
198        pitimer.writeCounter(0, pkt->get<uint8_t>());
199        break;
200      case TSDEV_TMR1_DATA:
201        pitimer.writeCounter(1, pkt->get<uint8_t>());
202        break;
203      case TSDEV_TMR2_DATA:
204        pitimer.writeCounter(2, pkt->get<uint8_t>());
205        break;
206      case TSDEV_TMR_CTRL:
207        pitimer.writeControl(pkt->get<uint8_t>());
208        break;
209      case TSDEV_RTC_ADDR:
210        rtcAddr = pkt->get<uint8_t>();
211        break;
212      case TSDEV_RTC_DATA:
213        rtc.writeData(rtcAddr, pkt->get<uint8_t>());
214        break;
215      case TSDEV_KBD:
216      case TSDEV_DMA1_CMND:
217      case TSDEV_DMA2_CMND:
218      case TSDEV_DMA1_MMASK:
219      case TSDEV_DMA2_MMASK:
220      case TSDEV_PIC2_ACK:
221      case TSDEV_DMA1_RESET:
222      case TSDEV_DMA2_RESET:
223      case TSDEV_DMA1_MASK:
224      case TSDEV_DMA2_MASK:
225      case TSDEV_CTRL_PORTB:
226        break;
227      default:
228        panic("I/O Write - va%#x size %d data %#x\n", pkt->getAddr(), pkt->getSize(), pkt->get<uint8_t>());
229    }
230
231    pkt->makeAtomicResponse();
232    return pioDelay;
233}
234
235void
236TsunamiIO::postPIC(uint8_t bitvector)
237{
238    //PIC2 Is not implemented, because nothing of interest there
239    picr |= bitvector;
240    if (picr & mask1) {
241        tsunami->cchip->postDRIR(55);
242        DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
243    }
244}
245
246void
247TsunamiIO::clearPIC(uint8_t bitvector)
248{
249    //PIC2 Is not implemented, because nothing of interest there
250    picr &= ~bitvector;
251    if (!(picr & mask1)) {
252        tsunami->cchip->clearDRIR(55);
253        DPRINTF(Tsunami, "clearing pic interrupt to cchip\n");
254    }
255}
256
257void
258TsunamiIO::serialize(ostream &os)
259{
260    SERIALIZE_SCALAR(rtcAddr);
261    SERIALIZE_SCALAR(timerData);
262    SERIALIZE_SCALAR(mask1);
263    SERIALIZE_SCALAR(mask2);
264    SERIALIZE_SCALAR(mode1);
265    SERIALIZE_SCALAR(mode2);
266    SERIALIZE_SCALAR(picr);
267    SERIALIZE_SCALAR(picInterrupting);
268
269    // Serialize the timers
270    pitimer.serialize("pitimer", os);
271    rtc.serialize("rtc", os);
272}
273
274void
275TsunamiIO::unserialize(Checkpoint *cp, const string &section)
276{
277    UNSERIALIZE_SCALAR(rtcAddr);
278    UNSERIALIZE_SCALAR(timerData);
279    UNSERIALIZE_SCALAR(mask1);
280    UNSERIALIZE_SCALAR(mask2);
281    UNSERIALIZE_SCALAR(mode1);
282    UNSERIALIZE_SCALAR(mode2);
283    UNSERIALIZE_SCALAR(picr);
284    UNSERIALIZE_SCALAR(picInterrupting);
285
286    // Unserialize the timers
287    pitimer.unserialize("pitimer", cp, section);
288    rtc.unserialize("rtc", cp, section);
289}
290
291TsunamiIO *
292TsunamiIOParams::create()
293{
294    return new TsunamiIO(this);
295}
296