tsunami_io.cc revision 769
1/* $Id$ */ 2 3/* @file 4 * Tsunami DMA fake 5 */ 6 7#include <deque> 8#include <string> 9#include <vector> 10 11#include "base/trace.hh" 12#include "cpu/exec_context.hh" 13#include "dev/console.hh" 14#include "dev/etherdev.hh" 15#include "dev/scsi_ctrl.hh" 16#include "dev/tlaser_clock.hh" 17#include "dev/tsunami_dma.hh" 18#include "dev/tsunamireg.h" 19#include "dev/tsunami.hh" 20#include "mem/functional_mem/memory_control.hh" 21#include "sim/builder.hh" 22#include "sim/system.hh" 23 24using namespace std; 25 26TsunamiDMA::TsunamiDMA(const string &name, /*Tsunami *t,*/ 27 Addr addr, Addr mask, MemoryController *mmu) 28 : MmapDevice(name, addr, mask, mmu)/*, tsunami(t) */ 29{ 30 31} 32 33Fault 34TsunamiDMA::read(MemReqPtr req, uint8_t *data) 35{ 36 DPRINTF(Tsunami, "dma read va=%#x size=%d IOPorrt=%#x\n", 37 req->vaddr, req->size, req->vaddr & 0xfff); 38 39 // Addr daddr = (req->paddr & addr_mask) >> 6; 40// ExecContext *xc = req->xc; 41// int cpuid = xc->cpu_id; 42 panic("I/O Read - va%#x size %d\n", req->vaddr, req->size); 43 // *(uint64_t*)data = 0x00; 44 45 return No_Fault; 46} 47 48Fault 49TsunamiDMA::write(MemReqPtr req, const uint8_t *data) 50{ 51 DPRINTF(Tsunami, "dma write - va=%#x size=%d IOPort=%#x\n", 52 req->vaddr, req->size, req->vaddr & 0xfff); 53 54 Addr daddr = (req->paddr & addr_mask); 55 56 switch(req->size) { 57 case sizeof(uint8_t): 58 switch(daddr) { 59 case TSDEV_PIC1_MASK: 60 mask1 = *(uint8_t*)data; 61 return No_Fault; 62 case TSDEV_PIC2_MASK: 63 mask2 = *(uint8_t*)data; 64 return No_Fault; 65 case TSDEV_DMA1_RESET: 66 return No_Fault; 67 case TSDEV_DMA2_RESET: 68 return No_Fault; 69 case TSDEV_DMA1_MODE: 70 mode1 = *(uint8_t*)data; 71 return No_Fault; 72 case TSDEV_DMA2_MODE: 73 mode2 = *(uint8_t*)data; 74 return No_Fault; 75 case TSDEV_DMA1_MASK: 76 case TSDEV_DMA2_MASK: 77 return No_Fault; 78 default: 79 panic("I/O Write - va%#x size %d\n", req->vaddr, req->size); 80 } 81 case sizeof(uint16_t): 82 case sizeof(uint32_t): 83 case sizeof(uint64_t): 84 default: 85 panic("I/O Write - invalid size - va %#x size %d\n", req->vaddr, req->size); 86 } 87 88 89 return No_Fault; 90} 91 92void 93TsunamiDMA::serialize(std::ostream &os) 94{ 95 // code should be written 96} 97 98void 99TsunamiDMA::unserialize(Checkpoint *cp, const std::string §ion) 100{ 101 //code should be written 102} 103 104BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiDMA) 105 106 // SimObjectParam<Tsunami *> tsunami; 107 SimObjectParam<MemoryController *> mmu; 108 Param<Addr> addr; 109 Param<Addr> mask; 110 111END_DECLARE_SIM_OBJECT_PARAMS(TsunamiDMA) 112 113BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiDMA) 114 115// INIT_PARAM(tsunami, "Tsunami"), 116 INIT_PARAM(mmu, "Memory Controller"), 117 INIT_PARAM(addr, "Device Address"), 118 INIT_PARAM(mask, "Address Mask") 119 120END_INIT_SIM_OBJECT_PARAMS(TsunamiDMA) 121 122CREATE_SIM_OBJECT(TsunamiDMA) 123{ 124 return new TsunamiDMA(getInstanceName(), /*tsunami,*/ addr, mask, mmu); 125} 126 127REGISTER_SIM_OBJECT("TsunamiDMA", TsunamiDMA) 128