tsunami_io.cc revision 3932:62e915bb6704
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 * Andrew Schultz 30 * Miguel Serrano 31 */ 32 33/** @file 34 * Tsunami I/O including PIC, PIT, RTC, DMA 35 */ 36 37#include <sys/time.h> 38 39#include <deque> 40#include <string> 41#include <vector> 42 43#include "base/trace.hh" 44#include "dev/pitreg.h" 45#include "dev/rtcreg.h" 46#include "dev/alpha/tsunami_cchip.hh" 47#include "dev/alpha/tsunami.hh" 48#include "dev/alpha/tsunami_io.hh" 49#include "dev/alpha/tsunamireg.h" 50#include "mem/packet.hh" 51#include "mem/packet_access.hh" 52#include "mem/port.hh" 53#include "sim/builder.hh" 54#include "sim/system.hh" 55 56using namespace std; 57//Should this be AlphaISA? 58using namespace TheISA; 59 60TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami, const vector<int> &t, 61 bool bcd, Tick i) 62 : _name(n), event(tsunami, i), addr(0), year_is_bcd(bcd) 63{ 64 memset(clock_data, 0, sizeof(clock_data)); 65 stat_regA = RTCA_32768HZ | RTCA_1024HZ; 66 stat_regB = RTCB_PRDC_IE |RTCB_BIN | RTCB_24HR; 67 68 if (year_is_bcd) { 69 // The RTC uses BCD for the last two digits in the year. 70 // They python year is a full year. 71 int _year = t[0] % 100; 72 int tens = _year / 10; 73 int ones = _year % 10; 74 75 year = (tens << 4) + ones; 76 } else { 77 // Even though the datasheet says that the year field should be 78 // interpreted as BCD, we just enter the number of years since 79 // 1900 since linux seems to be happy with that (and I believe 80 // that Tru64 was as well) 81 year = t[0] - 1900; 82 } 83 84 mon = t[1]; 85 mday = t[2]; 86 hour = t[3]; 87 min = t[4]; 88 sec = t[5]; 89 90 // wday is defined to be in the range from 1 - 7 with 1 being Sunday. 91 // the value coming from python is in the range from 0 - 6 with 0 being 92 // Monday. Fix that here. 93 wday = t[6] + 2; 94 if (wday > 7) 95 wday -= 7; 96 97 DPRINTFN("Real-time clock set to %s", getDateString()); 98} 99 100std::string 101TsunamiIO::RTC::getDateString() 102{ 103 struct tm tm; 104 105 memset(&tm, 0, sizeof(tm)); 106 107 if (year_is_bcd) { 108 // undo the BCD and conver to years since 1900 guessing that 109 // anything before 1970 is actually after 2000 110 int _year = (year >> 4) * 10 + (year & 0xf); 111 if (_year < 70) 112 _year += 100; 113 114 tm.tm_year = _year; 115 } else { 116 // number of years since 1900 117 tm.tm_year = year; 118 } 119 120 // unix is 0-11 for month 121 tm.tm_mon = mon - 1; 122 tm.tm_mday = mday; 123 tm.tm_hour = hour; 124 tm.tm_min = min; 125 tm.tm_sec = sec; 126 127 // to add more annoyance unix is 0 - 6 with 0 as sunday 128 tm.tm_wday = wday - 1; 129 130 return asctime(&tm); 131} 132 133void 134TsunamiIO::RTC::writeAddr(const uint8_t data) 135{ 136 if (data <= RTC_STAT_REGD) 137 addr = data; 138 else 139 panic("RTC addresses over 0xD are not implemented.\n"); 140} 141 142void 143TsunamiIO::RTC::writeData(const uint8_t data) 144{ 145 if (addr < RTC_STAT_REGA) 146 clock_data[addr] = data; 147 else { 148 switch (addr) { 149 case RTC_STAT_REGA: 150 if (data != (RTCA_32768HZ | RTCA_1024HZ)) 151 panic("Unimplemented RTC register A value write!\n"); 152 stat_regA = data; 153 break; 154 case RTC_STAT_REGB: 155 if ((data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != (RTCB_BIN | RTCB_24HR)) 156 panic("Write to RTC reg B bits that are not implemented!\n"); 157 158 if (data & RTCB_PRDC_IE) { 159 if (!event.scheduled()) 160 event.scheduleIntr(); 161 } else { 162 if (event.scheduled()) 163 event.deschedule(); 164 } 165 stat_regB = data; 166 break; 167 case RTC_STAT_REGC: 168 case RTC_STAT_REGD: 169 panic("RTC status registers C and D are not implemented.\n"); 170 break; 171 } 172 } 173} 174 175uint8_t 176TsunamiIO::RTC::readData() 177{ 178 if (addr < RTC_STAT_REGA) 179 return clock_data[addr]; 180 else { 181 switch (addr) { 182 case RTC_STAT_REGA: 183 // toggle UIP bit for linux 184 stat_regA ^= RTCA_UIP; 185 return stat_regA; 186 break; 187 case RTC_STAT_REGB: 188 return stat_regB; 189 break; 190 case RTC_STAT_REGC: 191 case RTC_STAT_REGD: 192 return 0x00; 193 break; 194 default: 195 panic("Shouldn't be here"); 196 } 197 } 198} 199 200void 201TsunamiIO::RTC::serialize(const string &base, ostream &os) 202{ 203 paramOut(os, base + ".addr", addr); 204 arrayParamOut(os, base + ".clock_data", clock_data, sizeof(clock_data)); 205 paramOut(os, base + ".stat_regA", stat_regA); 206 paramOut(os, base + ".stat_regB", stat_regB); 207} 208 209void 210TsunamiIO::RTC::unserialize(const string &base, Checkpoint *cp, 211 const string §ion) 212{ 213 paramIn(cp, section, base + ".addr", addr); 214 arrayParamIn(cp, section, base + ".clock_data", clock_data, 215 sizeof(clock_data)); 216 paramIn(cp, section, base + ".stat_regA", stat_regA); 217 paramIn(cp, section, base + ".stat_regB", stat_regB); 218 219 // We're not unserializing the event here, but we need to 220 // rescehedule the event since curTick was moved forward by the 221 // checkpoint 222 event.reschedule(curTick + event.interval); 223} 224 225TsunamiIO::RTC::RTCEvent::RTCEvent(Tsunami*t, Tick i) 226 : Event(&mainEventQueue), tsunami(t), interval(i) 227{ 228 DPRINTF(MC146818, "RTC Event Initilizing\n"); 229 schedule(curTick + interval); 230} 231 232void 233TsunamiIO::RTC::RTCEvent::scheduleIntr() 234{ 235 schedule(curTick + interval); 236} 237 238void 239TsunamiIO::RTC::RTCEvent::process() 240{ 241 DPRINTF(MC146818, "RTC Timer Interrupt\n"); 242 schedule(curTick + interval); 243 //Actually interrupt the processor here 244 tsunami->cchip->postRTC(); 245} 246 247const char * 248TsunamiIO::RTC::RTCEvent::description() 249{ 250 return "tsunami RTC interrupt"; 251} 252 253TsunamiIO::PITimer::PITimer(const string &name) 254 : _name(name), counter0(name + ".counter0"), counter1(name + ".counter1"), 255 counter2(name + ".counter2") 256{ 257 counter[0] = &counter0; 258 counter[1] = &counter0; 259 counter[2] = &counter0; 260} 261 262void 263TsunamiIO::PITimer::writeControl(const uint8_t data) 264{ 265 int rw; 266 int sel; 267 268 sel = GET_CTRL_SEL(data); 269 270 if (sel == PIT_READ_BACK) 271 panic("PITimer Read-Back Command is not implemented.\n"); 272 273 rw = GET_CTRL_RW(data); 274 275 if (rw == PIT_RW_LATCH_COMMAND) 276 counter[sel]->latchCount(); 277 else { 278 counter[sel]->setRW(rw); 279 counter[sel]->setMode(GET_CTRL_MODE(data)); 280 counter[sel]->setBCD(GET_CTRL_BCD(data)); 281 } 282} 283 284void 285TsunamiIO::PITimer::serialize(const string &base, ostream &os) 286{ 287 // serialize the counters 288 counter0.serialize(base + ".counter0", os); 289 counter1.serialize(base + ".counter1", os); 290 counter2.serialize(base + ".counter2", os); 291} 292 293void 294TsunamiIO::PITimer::unserialize(const string &base, Checkpoint *cp, 295 const string §ion) 296{ 297 // unserialze the counters 298 counter0.unserialize(base + ".counter0", cp, section); 299 counter1.unserialize(base + ".counter1", cp, section); 300 counter2.unserialize(base + ".counter2", cp, section); 301} 302 303TsunamiIO::PITimer::Counter::Counter(const string &name) 304 : _name(name), event(this), count(0), latched_count(0), period(0), 305 mode(0), output_high(false), latch_on(false), read_byte(LSB), 306 write_byte(LSB) 307{ 308 309} 310 311void 312TsunamiIO::PITimer::Counter::latchCount() 313{ 314 // behave like a real latch 315 if(!latch_on) { 316 latch_on = true; 317 read_byte = LSB; 318 latched_count = count; 319 } 320} 321 322uint8_t 323TsunamiIO::PITimer::Counter::read() 324{ 325 if (latch_on) { 326 switch (read_byte) { 327 case LSB: 328 read_byte = MSB; 329 return (uint8_t)latched_count; 330 break; 331 case MSB: 332 read_byte = LSB; 333 latch_on = false; 334 return latched_count >> 8; 335 break; 336 default: 337 panic("Shouldn't be here"); 338 } 339 } else { 340 switch (read_byte) { 341 case LSB: 342 read_byte = MSB; 343 return (uint8_t)count; 344 break; 345 case MSB: 346 read_byte = LSB; 347 return count >> 8; 348 break; 349 default: 350 panic("Shouldn't be here"); 351 } 352 } 353} 354 355void 356TsunamiIO::PITimer::Counter::write(const uint8_t data) 357{ 358 switch (write_byte) { 359 case LSB: 360 count = (count & 0xFF00) | data; 361 362 if (event.scheduled()) 363 event.deschedule(); 364 output_high = false; 365 write_byte = MSB; 366 break; 367 368 case MSB: 369 count = (count & 0x00FF) | (data << 8); 370 period = count; 371 372 if (period > 0) { 373 DPRINTF(Tsunami, "Timer set to curTick + %d\n", 374 count * event.interval); 375 event.schedule(curTick + count * event.interval); 376 } 377 write_byte = LSB; 378 break; 379 } 380} 381 382void 383TsunamiIO::PITimer::Counter::setRW(int rw_val) 384{ 385 if (rw_val != PIT_RW_16BIT) 386 panic("Only LSB/MSB read/write is implemented.\n"); 387} 388 389void 390TsunamiIO::PITimer::Counter::setMode(int mode_val) 391{ 392 if(mode_val != PIT_MODE_INTTC && mode_val != PIT_MODE_RATEGEN && 393 mode_val != PIT_MODE_SQWAVE) 394 panic("PIT mode %#x is not implemented: \n", mode_val); 395 396 mode = mode_val; 397} 398 399void 400TsunamiIO::PITimer::Counter::setBCD(int bcd_val) 401{ 402 if (bcd_val != PIT_BCD_FALSE) 403 panic("PITimer does not implement BCD counts.\n"); 404} 405 406bool 407TsunamiIO::PITimer::Counter::outputHigh() 408{ 409 return output_high; 410} 411 412void 413TsunamiIO::PITimer::Counter::serialize(const string &base, ostream &os) 414{ 415 paramOut(os, base + ".count", count); 416 paramOut(os, base + ".latched_count", latched_count); 417 paramOut(os, base + ".period", period); 418 paramOut(os, base + ".mode", mode); 419 paramOut(os, base + ".output_high", output_high); 420 paramOut(os, base + ".latch_on", latch_on); 421 paramOut(os, base + ".read_byte", read_byte); 422 paramOut(os, base + ".write_byte", write_byte); 423 424 Tick event_tick = 0; 425 if (event.scheduled()) 426 event_tick = event.when(); 427 paramOut(os, base + ".event_tick", event_tick); 428} 429 430void 431TsunamiIO::PITimer::Counter::unserialize(const string &base, Checkpoint *cp, 432 const string §ion) 433{ 434 paramIn(cp, section, base + ".count", count); 435 paramIn(cp, section, base + ".latched_count", latched_count); 436 paramIn(cp, section, base + ".period", period); 437 paramIn(cp, section, base + ".mode", mode); 438 paramIn(cp, section, base + ".output_high", output_high); 439 paramIn(cp, section, base + ".latch_on", latch_on); 440 paramIn(cp, section, base + ".read_byte", read_byte); 441 paramIn(cp, section, base + ".write_byte", write_byte); 442 443 Tick event_tick; 444 paramIn(cp, section, base + ".event_tick", event_tick); 445 if (event_tick) 446 event.schedule(event_tick); 447} 448 449TsunamiIO::PITimer::Counter::CounterEvent::CounterEvent(Counter* c_ptr) 450 : Event(&mainEventQueue) 451{ 452 interval = (Tick)(Clock::Float::s / 1193180.0); 453 counter = c_ptr; 454} 455 456void 457TsunamiIO::PITimer::Counter::CounterEvent::process() 458{ 459 DPRINTF(Tsunami, "Timer Interrupt\n"); 460 switch (counter->mode) { 461 case PIT_MODE_INTTC: 462 counter->output_high = true; 463 case PIT_MODE_RATEGEN: 464 case PIT_MODE_SQWAVE: 465 break; 466 default: 467 panic("Unimplemented PITimer mode.\n"); 468 } 469} 470 471const char * 472TsunamiIO::PITimer::Counter::CounterEvent::description() 473{ 474 return "tsunami 8254 Interval timer"; 475} 476 477TsunamiIO::TsunamiIO(Params *p) 478 : BasicPioDevice(p), tsunami(p->tsunami), pitimer(p->name + "pitimer"), 479 rtc(p->name + ".rtc", p->tsunami, p->init_time, p->year_is_bcd, 480 p->frequency) 481{ 482 pioSize = 0x100; 483 484 // set the back pointer from tsunami to myself 485 tsunami->io = this; 486 487 timerData = 0; 488 picr = 0; 489 picInterrupting = false; 490} 491 492Tick 493TsunamiIO::frequency() const 494{ 495 return Clock::Frequency / params()->frequency; 496} 497 498Tick 499TsunamiIO::read(PacketPtr pkt) 500{ 501 assert(pkt->result == Packet::Unknown); 502 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 503 504 Addr daddr = pkt->getAddr() - pioAddr; 505 506 DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(), 507 pkt->getSize(), daddr); 508 509 pkt->allocate(); 510 511 if (pkt->getSize() == sizeof(uint8_t)) { 512 switch(daddr) { 513 // PIC1 mask read 514 case TSDEV_PIC1_MASK: 515 pkt->set(~mask1); 516 break; 517 case TSDEV_PIC2_MASK: 518 pkt->set(~mask2); 519 break; 520 case TSDEV_PIC1_ISR: 521 // !!! If this is modified 64bit case needs to be too 522 // Pal code has to do a 64 bit physical read because there is 523 // no load physical byte instruction 524 pkt->set(picr); 525 break; 526 case TSDEV_PIC2_ISR: 527 // PIC2 not implemnted... just return 0 528 pkt->set(0x00); 529 break; 530 case TSDEV_TMR0_DATA: 531 pkt->set(pitimer.counter0.read()); 532 break; 533 case TSDEV_TMR1_DATA: 534 pkt->set(pitimer.counter1.read()); 535 break; 536 case TSDEV_TMR2_DATA: 537 pkt->set(pitimer.counter2.read()); 538 break; 539 case TSDEV_RTC_DATA: 540 pkt->set(rtc.readData()); 541 break; 542 case TSDEV_CTRL_PORTB: 543 if (pitimer.counter2.outputHigh()) 544 pkt->set(PORTB_SPKR_HIGH); 545 else 546 pkt->set(0x00); 547 break; 548 default: 549 panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize()); 550 } 551 } else if (pkt->getSize() == sizeof(uint64_t)) { 552 if (daddr == TSDEV_PIC1_ISR) 553 pkt->set<uint64_t>(picr); 554 else 555 panic("I/O Read - invalid addr - va %#x size %d\n", 556 pkt->getAddr(), pkt->getSize()); 557 } else { 558 panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize()); 559 } 560 pkt->result = Packet::Success; 561 return pioDelay; 562} 563 564Tick 565TsunamiIO::write(PacketPtr pkt) 566{ 567 assert(pkt->result == Packet::Unknown); 568 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 569 Addr daddr = pkt->getAddr() - pioAddr; 570 571 DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n", 572 pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff, (uint32_t)pkt->get<uint8_t>()); 573 574 assert(pkt->getSize() == sizeof(uint8_t)); 575 576 switch(daddr) { 577 case TSDEV_PIC1_MASK: 578 mask1 = ~(pkt->get<uint8_t>()); 579 if ((picr & mask1) && !picInterrupting) { 580 picInterrupting = true; 581 tsunami->cchip->postDRIR(55); 582 DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); 583 } 584 if ((!(picr & mask1)) && picInterrupting) { 585 picInterrupting = false; 586 tsunami->cchip->clearDRIR(55); 587 DPRINTF(Tsunami, "clearing pic interrupt\n"); 588 } 589 break; 590 case TSDEV_PIC2_MASK: 591 mask2 = pkt->get<uint8_t>(); 592 //PIC2 Not implemented to interrupt 593 break; 594 case TSDEV_PIC1_ACK: 595 // clear the interrupt on the PIC 596 picr &= ~(1 << (pkt->get<uint8_t>() & 0xF)); 597 if (!(picr & mask1)) 598 tsunami->cchip->clearDRIR(55); 599 break; 600 case TSDEV_DMA1_MODE: 601 mode1 = pkt->get<uint8_t>(); 602 break; 603 case TSDEV_DMA2_MODE: 604 mode2 = pkt->get<uint8_t>(); 605 break; 606 case TSDEV_TMR0_DATA: 607 pitimer.counter0.write(pkt->get<uint8_t>()); 608 break; 609 case TSDEV_TMR1_DATA: 610 pitimer.counter1.write(pkt->get<uint8_t>()); 611 break; 612 case TSDEV_TMR2_DATA: 613 pitimer.counter2.write(pkt->get<uint8_t>()); 614 break; 615 case TSDEV_TMR_CTRL: 616 pitimer.writeControl(pkt->get<uint8_t>()); 617 break; 618 case TSDEV_RTC_ADDR: 619 rtc.writeAddr(pkt->get<uint8_t>()); 620 break; 621 case TSDEV_RTC_DATA: 622 rtc.writeData(pkt->get<uint8_t>()); 623 break; 624 case TSDEV_KBD: 625 case TSDEV_DMA1_CMND: 626 case TSDEV_DMA2_CMND: 627 case TSDEV_DMA1_MMASK: 628 case TSDEV_DMA2_MMASK: 629 case TSDEV_PIC2_ACK: 630 case TSDEV_DMA1_RESET: 631 case TSDEV_DMA2_RESET: 632 case TSDEV_DMA1_MASK: 633 case TSDEV_DMA2_MASK: 634 case TSDEV_CTRL_PORTB: 635 break; 636 default: 637 panic("I/O Write - va%#x size %d data %#x\n", pkt->getAddr(), pkt->getSize(), pkt->get<uint8_t>()); 638 } 639 640 pkt->result = Packet::Success; 641 return pioDelay; 642} 643 644void 645TsunamiIO::postPIC(uint8_t bitvector) 646{ 647 //PIC2 Is not implemented, because nothing of interest there 648 picr |= bitvector; 649 if (picr & mask1) { 650 tsunami->cchip->postDRIR(55); 651 DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); 652 } 653} 654 655void 656TsunamiIO::clearPIC(uint8_t bitvector) 657{ 658 //PIC2 Is not implemented, because nothing of interest there 659 picr &= ~bitvector; 660 if (!(picr & mask1)) { 661 tsunami->cchip->clearDRIR(55); 662 DPRINTF(Tsunami, "clearing pic interrupt to cchip\n"); 663 } 664} 665 666void 667TsunamiIO::serialize(ostream &os) 668{ 669 SERIALIZE_SCALAR(timerData); 670 SERIALIZE_SCALAR(mask1); 671 SERIALIZE_SCALAR(mask2); 672 SERIALIZE_SCALAR(mode1); 673 SERIALIZE_SCALAR(mode2); 674 SERIALIZE_SCALAR(picr); 675 SERIALIZE_SCALAR(picInterrupting); 676 677 // Serialize the timers 678 pitimer.serialize("pitimer", os); 679 rtc.serialize("rtc", os); 680} 681 682void 683TsunamiIO::unserialize(Checkpoint *cp, const string §ion) 684{ 685 UNSERIALIZE_SCALAR(timerData); 686 UNSERIALIZE_SCALAR(mask1); 687 UNSERIALIZE_SCALAR(mask2); 688 UNSERIALIZE_SCALAR(mode1); 689 UNSERIALIZE_SCALAR(mode2); 690 UNSERIALIZE_SCALAR(picr); 691 UNSERIALIZE_SCALAR(picInterrupting); 692 693 // Unserialize the timers 694 pitimer.unserialize("pitimer", cp, section); 695 rtc.unserialize("rtc", cp, section); 696} 697 698BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO) 699 700 Param<Addr> pio_addr; 701 Param<Tick> pio_latency; 702 Param<Tick> frequency; 703 SimObjectParam<Platform *> platform; 704 SimObjectParam<System *> system; 705 VectorParam<int> time; 706 Param<bool> year_is_bcd; 707 SimObjectParam<Tsunami *> tsunami; 708 709END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO) 710 711BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO) 712 713 INIT_PARAM(pio_addr, "Device Address"), 714 INIT_PARAM(pio_latency, "Programmed IO latency"), 715 INIT_PARAM(frequency, "clock interrupt frequency"), 716 INIT_PARAM(platform, "platform"), 717 INIT_PARAM(system, "system object"), 718 INIT_PARAM(time, "System time to use (0 for actual time"), 719 INIT_PARAM(year_is_bcd, ""), 720 INIT_PARAM(tsunami, "Tsunami") 721 722END_INIT_SIM_OBJECT_PARAMS(TsunamiIO) 723 724CREATE_SIM_OBJECT(TsunamiIO) 725{ 726 TsunamiIO::Params *p = new TsunamiIO::Params; 727 p->frequency = frequency; 728 p->name = getInstanceName(); 729 p->pio_addr = pio_addr; 730 p->pio_delay = pio_latency; 731 p->platform = platform; 732 p->system = system; 733 p->init_time = time; 734 p->year_is_bcd = year_is_bcd; 735 p->tsunami = tsunami; 736 return new TsunamiIO(p); 737} 738 739REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO) 740