tsunami_io.cc revision 9808
1803SN/A/* 21363SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 3803SN/A * All rights reserved. 4803SN/A * 5803SN/A * Redistribution and use in source and binary forms, with or without 6803SN/A * modification, are permitted provided that the following conditions are 7803SN/A * met: redistributions of source code must retain the above copyright 8803SN/A * notice, this list of conditions and the following disclaimer; 9803SN/A * redistributions in binary form must reproduce the above copyright 10803SN/A * notice, this list of conditions and the following disclaimer in the 11803SN/A * documentation and/or other materials provided with the distribution; 12803SN/A * neither the name of the copyright holders nor the names of its 13803SN/A * contributors may be used to endorse or promote products derived from 14803SN/A * this software without specific prior written permission. 15803SN/A * 16803SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17803SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18803SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19803SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20803SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21803SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22803SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23803SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24803SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25803SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26803SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Ali Saidi 292665SN/A * Andrew Schultz 302665SN/A * Miguel Serrano 31803SN/A */ 32768SN/A 331730SN/A/** @file 34773SN/A * Tsunami I/O including PIC, PIT, RTC, DMA 35768SN/A */ 36768SN/A 37773SN/A#include <sys/time.h> 38773SN/A 39768SN/A#include <deque> 40768SN/A#include <string> 41768SN/A#include <vector> 42768SN/A 434762Snate@binkert.org#include "base/time.hh" 44768SN/A#include "base/trace.hh" 456658Snate@binkert.org#include "config/the_isa.hh" 468232Snate@binkert.org#include "debug/Tsunami.hh" 478229Snate@binkert.org#include "dev/alpha/tsunami.hh" 483540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_cchip.hh" 493540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_io.hh" 503540Sgblack@eecs.umich.edu#include "dev/alpha/tsunamireg.h" 518229Snate@binkert.org#include "dev/rtcreg.h" 523348SN/A#include "mem/packet.hh" 533348SN/A#include "mem/packet_access.hh" 542542SN/A#include "mem/port.hh" 552542SN/A#include "sim/system.hh" 56768SN/A 578737Skoansin.tan@gmail.com// clang complains about std::set being overloaded with Packet::set if 588737Skoansin.tan@gmail.com// we open up the entire namespace std 598737Skoansin.tan@gmail.comusing std::string; 608737Skoansin.tan@gmail.comusing std::ostream; 618737Skoansin.tan@gmail.com 622107SN/A//Should this be AlphaISA? 632107SN/Ausing namespace TheISA; 64773SN/A 655606Snate@binkert.orgTsunamiIO::RTC::RTC(const string &n, const TsunamiIOParams *p) 665606Snate@binkert.org : MC146818(p->tsunami, n, p->time, p->year_is_bcd, p->frequency), 675606Snate@binkert.org tsunami(p->tsunami) 681817SN/A{ 69772SN/A} 70772SN/A 714762Snate@binkert.orgTsunamiIO::TsunamiIO(const Params *p) 729808Sstever@gmail.com : BasicPioDevice(p, 0x100), tsunami(p->tsunami), 735606Snate@binkert.org pitimer(this, p->name + "pitimer"), rtc(p->name + ".rtc", p) 74768SN/A{ 75803SN/A // set the back pointer from tsunami to myself 76803SN/A tsunami->io = this; 77803SN/A 78771SN/A timerData = 0; 79777SN/A picr = 0; 80777SN/A picInterrupting = false; 81773SN/A} 82773SN/A 831634SN/ATick 841634SN/ATsunamiIO::frequency() const 851634SN/A{ 867064Snate@binkert.org return SimClock::Frequency / params()->frequency; 871634SN/A} 881634SN/A 892542SN/ATick 903349SN/ATsunamiIO::read(PacketPtr pkt) 91768SN/A{ 922641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 93768SN/A 942641SN/A Addr daddr = pkt->getAddr() - pioAddr; 95865SN/A 962641SN/A DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(), 972641SN/A pkt->getSize(), daddr); 98771SN/A 992630SN/A pkt->allocate(); 1002539SN/A 1012641SN/A if (pkt->getSize() == sizeof(uint8_t)) { 102803SN/A switch(daddr) { 1031817SN/A // PIC1 mask read 1041817SN/A case TSDEV_PIC1_MASK: 1052630SN/A pkt->set(~mask1); 1062539SN/A break; 1071817SN/A case TSDEV_PIC2_MASK: 1082630SN/A pkt->set(~mask2); 1092539SN/A break; 110865SN/A case TSDEV_PIC1_ISR: 111865SN/A // !!! If this is modified 64bit case needs to be too 112865SN/A // Pal code has to do a 64 bit physical read because there is 113865SN/A // no load physical byte instruction 1142630SN/A pkt->set(picr); 1152539SN/A break; 116865SN/A case TSDEV_PIC2_ISR: 117865SN/A // PIC2 not implemnted... just return 0 1182630SN/A pkt->set(0x00); 1192539SN/A break; 1201817SN/A case TSDEV_TMR0_DATA: 1215635Sgblack@eecs.umich.edu pkt->set(pitimer.readCounter(0)); 1222542SN/A break; 1231817SN/A case TSDEV_TMR1_DATA: 1245635Sgblack@eecs.umich.edu pkt->set(pitimer.readCounter(1)); 1252542SN/A break; 1261817SN/A case TSDEV_TMR2_DATA: 1275635Sgblack@eecs.umich.edu pkt->set(pitimer.readCounter(2)); 1282539SN/A break; 129803SN/A case TSDEV_RTC_DATA: 1305392Sgblack@eecs.umich.edu pkt->set(rtc.readData(rtcAddr)); 1312539SN/A break; 1321817SN/A case TSDEV_CTRL_PORTB: 1335635Sgblack@eecs.umich.edu if (pitimer.outputHigh(2)) 1342630SN/A pkt->set(PORTB_SPKR_HIGH); 1351817SN/A else 1362630SN/A pkt->set(0x00); 1372539SN/A break; 138803SN/A default: 1392641SN/A panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize()); 140803SN/A } 1412641SN/A } else if (pkt->getSize() == sizeof(uint64_t)) { 1422539SN/A if (daddr == TSDEV_PIC1_ISR) 1432630SN/A pkt->set<uint64_t>(picr); 1442539SN/A else 1452539SN/A panic("I/O Read - invalid addr - va %#x size %d\n", 1462641SN/A pkt->getAddr(), pkt->getSize()); 1472539SN/A } else { 1482641SN/A panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize()); 149771SN/A } 1504870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 1512539SN/A return pioDelay; 152768SN/A} 153768SN/A 1542539SN/ATick 1553349SN/ATsunamiIO::write(PacketPtr pkt) 156768SN/A{ 1572641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1582641SN/A Addr daddr = pkt->getAddr() - pioAddr; 159779SN/A 160779SN/A DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n", 1612641SN/A pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff, (uint32_t)pkt->get<uint8_t>()); 162768SN/A 1632641SN/A assert(pkt->getSize() == sizeof(uint8_t)); 164769SN/A 1652539SN/A switch(daddr) { 1662539SN/A case TSDEV_PIC1_MASK: 1672630SN/A mask1 = ~(pkt->get<uint8_t>()); 1682539SN/A if ((picr & mask1) && !picInterrupting) { 1692539SN/A picInterrupting = true; 1702539SN/A tsunami->cchip->postDRIR(55); 1712539SN/A DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); 172803SN/A } 1732539SN/A if ((!(picr & mask1)) && picInterrupting) { 1742539SN/A picInterrupting = false; 1752539SN/A tsunami->cchip->clearDRIR(55); 1762539SN/A DPRINTF(Tsunami, "clearing pic interrupt\n"); 1772539SN/A } 1782539SN/A break; 1792539SN/A case TSDEV_PIC2_MASK: 1802630SN/A mask2 = pkt->get<uint8_t>(); 1812539SN/A //PIC2 Not implemented to interrupt 1822539SN/A break; 1832539SN/A case TSDEV_PIC1_ACK: 1842539SN/A // clear the interrupt on the PIC 1852630SN/A picr &= ~(1 << (pkt->get<uint8_t>() & 0xF)); 1862539SN/A if (!(picr & mask1)) 1872539SN/A tsunami->cchip->clearDRIR(55); 1882539SN/A break; 1892539SN/A case TSDEV_DMA1_MODE: 1902630SN/A mode1 = pkt->get<uint8_t>(); 1912539SN/A break; 1922539SN/A case TSDEV_DMA2_MODE: 1932630SN/A mode2 = pkt->get<uint8_t>(); 1942539SN/A break; 1952539SN/A case TSDEV_TMR0_DATA: 1965635Sgblack@eecs.umich.edu pitimer.writeCounter(0, pkt->get<uint8_t>()); 1972539SN/A break; 1982539SN/A case TSDEV_TMR1_DATA: 1995635Sgblack@eecs.umich.edu pitimer.writeCounter(1, pkt->get<uint8_t>()); 2002539SN/A break; 2012539SN/A case TSDEV_TMR2_DATA: 2025635Sgblack@eecs.umich.edu pitimer.writeCounter(2, pkt->get<uint8_t>()); 2032539SN/A break; 2042539SN/A case TSDEV_TMR_CTRL: 2052630SN/A pitimer.writeControl(pkt->get<uint8_t>()); 2062539SN/A break; 2072539SN/A case TSDEV_RTC_ADDR: 2085392Sgblack@eecs.umich.edu rtcAddr = pkt->get<uint8_t>(); 2092539SN/A break; 2102539SN/A case TSDEV_RTC_DATA: 2115392Sgblack@eecs.umich.edu rtc.writeData(rtcAddr, pkt->get<uint8_t>()); 2122539SN/A break; 2132539SN/A case TSDEV_KBD: 2142539SN/A case TSDEV_DMA1_CMND: 2152539SN/A case TSDEV_DMA2_CMND: 2162539SN/A case TSDEV_DMA1_MMASK: 2172539SN/A case TSDEV_DMA2_MMASK: 2182539SN/A case TSDEV_PIC2_ACK: 2192539SN/A case TSDEV_DMA1_RESET: 2202539SN/A case TSDEV_DMA2_RESET: 2212539SN/A case TSDEV_DMA1_MASK: 2222539SN/A case TSDEV_DMA2_MASK: 2232539SN/A case TSDEV_CTRL_PORTB: 2242539SN/A break; 225803SN/A default: 2262641SN/A panic("I/O Write - va%#x size %d data %#x\n", pkt->getAddr(), pkt->getSize(), pkt->get<uint8_t>()); 227769SN/A } 228769SN/A 2294870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 2302539SN/A return pioDelay; 231768SN/A} 232768SN/A 233768SN/Avoid 234777SN/ATsunamiIO::postPIC(uint8_t bitvector) 235777SN/A{ 236777SN/A //PIC2 Is not implemented, because nothing of interest there 237777SN/A picr |= bitvector; 238865SN/A if (picr & mask1) { 239817SN/A tsunami->cchip->postDRIR(55); 240777SN/A DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); 241777SN/A } 242777SN/A} 243777SN/A 244777SN/Avoid 245777SN/ATsunamiIO::clearPIC(uint8_t bitvector) 246777SN/A{ 247777SN/A //PIC2 Is not implemented, because nothing of interest there 248777SN/A picr &= ~bitvector; 249777SN/A if (!(picr & mask1)) { 250817SN/A tsunami->cchip->clearDRIR(55); 251777SN/A DPRINTF(Tsunami, "clearing pic interrupt to cchip\n"); 252777SN/A } 253777SN/A} 254777SN/A 255777SN/Avoid 2561854SN/ATsunamiIO::serialize(ostream &os) 257768SN/A{ 2585392Sgblack@eecs.umich.edu SERIALIZE_SCALAR(rtcAddr); 259811SN/A SERIALIZE_SCALAR(timerData); 260899SN/A SERIALIZE_SCALAR(mask1); 261899SN/A SERIALIZE_SCALAR(mask2); 262899SN/A SERIALIZE_SCALAR(mode1); 263899SN/A SERIALIZE_SCALAR(mode2); 264811SN/A SERIALIZE_SCALAR(picr); 265811SN/A SERIALIZE_SCALAR(picInterrupting); 266811SN/A 267919SN/A // Serialize the timers 2681854SN/A pitimer.serialize("pitimer", os); 2691854SN/A rtc.serialize("rtc", os); 270768SN/A} 271768SN/A 272768SN/Avoid 2731854SN/ATsunamiIO::unserialize(Checkpoint *cp, const string §ion) 274768SN/A{ 2755392Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(rtcAddr); 276811SN/A UNSERIALIZE_SCALAR(timerData); 277899SN/A UNSERIALIZE_SCALAR(mask1); 278899SN/A UNSERIALIZE_SCALAR(mask2); 279899SN/A UNSERIALIZE_SCALAR(mode1); 280899SN/A UNSERIALIZE_SCALAR(mode2); 281811SN/A UNSERIALIZE_SCALAR(picr); 282811SN/A UNSERIALIZE_SCALAR(picInterrupting); 283919SN/A 284919SN/A // Unserialize the timers 2851854SN/A pitimer.unserialize("pitimer", cp, section); 2861854SN/A rtc.unserialize("rtc", cp, section); 287768SN/A} 288768SN/A 2894762Snate@binkert.orgTsunamiIO * 2904762Snate@binkert.orgTsunamiIOParams::create() 291768SN/A{ 2924762Snate@binkert.org return new TsunamiIO(this); 293768SN/A} 294