tsunami_io.cc revision 8232
1803SN/A/* 21363SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 3803SN/A * All rights reserved. 4803SN/A * 5803SN/A * Redistribution and use in source and binary forms, with or without 6803SN/A * modification, are permitted provided that the following conditions are 7803SN/A * met: redistributions of source code must retain the above copyright 8803SN/A * notice, this list of conditions and the following disclaimer; 9803SN/A * redistributions in binary form must reproduce the above copyright 10803SN/A * notice, this list of conditions and the following disclaimer in the 11803SN/A * documentation and/or other materials provided with the distribution; 12803SN/A * neither the name of the copyright holders nor the names of its 13803SN/A * contributors may be used to endorse or promote products derived from 14803SN/A * this software without specific prior written permission. 15803SN/A * 16803SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17803SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18803SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19803SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20803SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21803SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22803SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23803SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24803SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25803SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26803SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Ali Saidi 292665SN/A * Andrew Schultz 302665SN/A * Miguel Serrano 31803SN/A */ 32768SN/A 331730SN/A/** @file 34773SN/A * Tsunami I/O including PIC, PIT, RTC, DMA 35768SN/A */ 36768SN/A 37773SN/A#include <sys/time.h> 38773SN/A 39768SN/A#include <deque> 40768SN/A#include <string> 41768SN/A#include <vector> 42768SN/A 434762Snate@binkert.org#include "base/time.hh" 44768SN/A#include "base/trace.hh" 456658Snate@binkert.org#include "config/the_isa.hh" 468232Snate@binkert.org#include "debug/Tsunami.hh" 478229Snate@binkert.org#include "dev/alpha/tsunami.hh" 483540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_cchip.hh" 493540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_io.hh" 503540Sgblack@eecs.umich.edu#include "dev/alpha/tsunamireg.h" 518229Snate@binkert.org#include "dev/rtcreg.h" 523348SN/A#include "mem/packet.hh" 533348SN/A#include "mem/packet_access.hh" 542542SN/A#include "mem/port.hh" 552542SN/A#include "sim/system.hh" 56768SN/A 57768SN/Ausing namespace std; 582107SN/A//Should this be AlphaISA? 592107SN/Ausing namespace TheISA; 60773SN/A 615606Snate@binkert.orgTsunamiIO::RTC::RTC(const string &n, const TsunamiIOParams *p) 625606Snate@binkert.org : MC146818(p->tsunami, n, p->time, p->year_is_bcd, p->frequency), 635606Snate@binkert.org tsunami(p->tsunami) 641817SN/A{ 65772SN/A} 66772SN/A 674762Snate@binkert.orgTsunamiIO::TsunamiIO(const Params *p) 685606Snate@binkert.org : BasicPioDevice(p), tsunami(p->tsunami), 695606Snate@binkert.org pitimer(this, p->name + "pitimer"), rtc(p->name + ".rtc", p) 70768SN/A{ 713846Shsul@eecs.umich.edu pioSize = 0x100; 72909SN/A 73803SN/A // set the back pointer from tsunami to myself 74803SN/A tsunami->io = this; 75803SN/A 76771SN/A timerData = 0; 77777SN/A picr = 0; 78777SN/A picInterrupting = false; 79773SN/A} 80773SN/A 811634SN/ATick 821634SN/ATsunamiIO::frequency() const 831634SN/A{ 847064Snate@binkert.org return SimClock::Frequency / params()->frequency; 851634SN/A} 861634SN/A 872542SN/ATick 883349SN/ATsunamiIO::read(PacketPtr pkt) 89768SN/A{ 902641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 91768SN/A 922641SN/A Addr daddr = pkt->getAddr() - pioAddr; 93865SN/A 942641SN/A DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(), 952641SN/A pkt->getSize(), daddr); 96771SN/A 972630SN/A pkt->allocate(); 982539SN/A 992641SN/A if (pkt->getSize() == sizeof(uint8_t)) { 100803SN/A switch(daddr) { 1011817SN/A // PIC1 mask read 1021817SN/A case TSDEV_PIC1_MASK: 1032630SN/A pkt->set(~mask1); 1042539SN/A break; 1051817SN/A case TSDEV_PIC2_MASK: 1062630SN/A pkt->set(~mask2); 1072539SN/A break; 108865SN/A case TSDEV_PIC1_ISR: 109865SN/A // !!! If this is modified 64bit case needs to be too 110865SN/A // Pal code has to do a 64 bit physical read because there is 111865SN/A // no load physical byte instruction 1122630SN/A pkt->set(picr); 1132539SN/A break; 114865SN/A case TSDEV_PIC2_ISR: 115865SN/A // PIC2 not implemnted... just return 0 1162630SN/A pkt->set(0x00); 1172539SN/A break; 1181817SN/A case TSDEV_TMR0_DATA: 1195635Sgblack@eecs.umich.edu pkt->set(pitimer.readCounter(0)); 1202542SN/A break; 1211817SN/A case TSDEV_TMR1_DATA: 1225635Sgblack@eecs.umich.edu pkt->set(pitimer.readCounter(1)); 1232542SN/A break; 1241817SN/A case TSDEV_TMR2_DATA: 1255635Sgblack@eecs.umich.edu pkt->set(pitimer.readCounter(2)); 1262539SN/A break; 127803SN/A case TSDEV_RTC_DATA: 1285392Sgblack@eecs.umich.edu pkt->set(rtc.readData(rtcAddr)); 1292539SN/A break; 1301817SN/A case TSDEV_CTRL_PORTB: 1315635Sgblack@eecs.umich.edu if (pitimer.outputHigh(2)) 1322630SN/A pkt->set(PORTB_SPKR_HIGH); 1331817SN/A else 1342630SN/A pkt->set(0x00); 1352539SN/A break; 136803SN/A default: 1372641SN/A panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize()); 138803SN/A } 1392641SN/A } else if (pkt->getSize() == sizeof(uint64_t)) { 1402539SN/A if (daddr == TSDEV_PIC1_ISR) 1412630SN/A pkt->set<uint64_t>(picr); 1422539SN/A else 1432539SN/A panic("I/O Read - invalid addr - va %#x size %d\n", 1442641SN/A pkt->getAddr(), pkt->getSize()); 1452539SN/A } else { 1462641SN/A panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize()); 147771SN/A } 1484870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 1492539SN/A return pioDelay; 150768SN/A} 151768SN/A 1522539SN/ATick 1533349SN/ATsunamiIO::write(PacketPtr pkt) 154768SN/A{ 1552641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1562641SN/A Addr daddr = pkt->getAddr() - pioAddr; 157779SN/A 158779SN/A DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n", 1592641SN/A pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff, (uint32_t)pkt->get<uint8_t>()); 160768SN/A 1612641SN/A assert(pkt->getSize() == sizeof(uint8_t)); 162769SN/A 1632539SN/A switch(daddr) { 1642539SN/A case TSDEV_PIC1_MASK: 1652630SN/A mask1 = ~(pkt->get<uint8_t>()); 1662539SN/A if ((picr & mask1) && !picInterrupting) { 1672539SN/A picInterrupting = true; 1682539SN/A tsunami->cchip->postDRIR(55); 1692539SN/A DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); 170803SN/A } 1712539SN/A if ((!(picr & mask1)) && picInterrupting) { 1722539SN/A picInterrupting = false; 1732539SN/A tsunami->cchip->clearDRIR(55); 1742539SN/A DPRINTF(Tsunami, "clearing pic interrupt\n"); 1752539SN/A } 1762539SN/A break; 1772539SN/A case TSDEV_PIC2_MASK: 1782630SN/A mask2 = pkt->get<uint8_t>(); 1792539SN/A //PIC2 Not implemented to interrupt 1802539SN/A break; 1812539SN/A case TSDEV_PIC1_ACK: 1822539SN/A // clear the interrupt on the PIC 1832630SN/A picr &= ~(1 << (pkt->get<uint8_t>() & 0xF)); 1842539SN/A if (!(picr & mask1)) 1852539SN/A tsunami->cchip->clearDRIR(55); 1862539SN/A break; 1872539SN/A case TSDEV_DMA1_MODE: 1882630SN/A mode1 = pkt->get<uint8_t>(); 1892539SN/A break; 1902539SN/A case TSDEV_DMA2_MODE: 1912630SN/A mode2 = pkt->get<uint8_t>(); 1922539SN/A break; 1932539SN/A case TSDEV_TMR0_DATA: 1945635Sgblack@eecs.umich.edu pitimer.writeCounter(0, pkt->get<uint8_t>()); 1952539SN/A break; 1962539SN/A case TSDEV_TMR1_DATA: 1975635Sgblack@eecs.umich.edu pitimer.writeCounter(1, pkt->get<uint8_t>()); 1982539SN/A break; 1992539SN/A case TSDEV_TMR2_DATA: 2005635Sgblack@eecs.umich.edu pitimer.writeCounter(2, pkt->get<uint8_t>()); 2012539SN/A break; 2022539SN/A case TSDEV_TMR_CTRL: 2032630SN/A pitimer.writeControl(pkt->get<uint8_t>()); 2042539SN/A break; 2052539SN/A case TSDEV_RTC_ADDR: 2065392Sgblack@eecs.umich.edu rtcAddr = pkt->get<uint8_t>(); 2072539SN/A break; 2082539SN/A case TSDEV_RTC_DATA: 2095392Sgblack@eecs.umich.edu rtc.writeData(rtcAddr, pkt->get<uint8_t>()); 2102539SN/A break; 2112539SN/A case TSDEV_KBD: 2122539SN/A case TSDEV_DMA1_CMND: 2132539SN/A case TSDEV_DMA2_CMND: 2142539SN/A case TSDEV_DMA1_MMASK: 2152539SN/A case TSDEV_DMA2_MMASK: 2162539SN/A case TSDEV_PIC2_ACK: 2172539SN/A case TSDEV_DMA1_RESET: 2182539SN/A case TSDEV_DMA2_RESET: 2192539SN/A case TSDEV_DMA1_MASK: 2202539SN/A case TSDEV_DMA2_MASK: 2212539SN/A case TSDEV_CTRL_PORTB: 2222539SN/A break; 223803SN/A default: 2242641SN/A panic("I/O Write - va%#x size %d data %#x\n", pkt->getAddr(), pkt->getSize(), pkt->get<uint8_t>()); 225769SN/A } 226769SN/A 2274870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 2282539SN/A return pioDelay; 229768SN/A} 230768SN/A 231768SN/Avoid 232777SN/ATsunamiIO::postPIC(uint8_t bitvector) 233777SN/A{ 234777SN/A //PIC2 Is not implemented, because nothing of interest there 235777SN/A picr |= bitvector; 236865SN/A if (picr & mask1) { 237817SN/A tsunami->cchip->postDRIR(55); 238777SN/A DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); 239777SN/A } 240777SN/A} 241777SN/A 242777SN/Avoid 243777SN/ATsunamiIO::clearPIC(uint8_t bitvector) 244777SN/A{ 245777SN/A //PIC2 Is not implemented, because nothing of interest there 246777SN/A picr &= ~bitvector; 247777SN/A if (!(picr & mask1)) { 248817SN/A tsunami->cchip->clearDRIR(55); 249777SN/A DPRINTF(Tsunami, "clearing pic interrupt to cchip\n"); 250777SN/A } 251777SN/A} 252777SN/A 253777SN/Avoid 2541854SN/ATsunamiIO::serialize(ostream &os) 255768SN/A{ 2565392Sgblack@eecs.umich.edu SERIALIZE_SCALAR(rtcAddr); 257811SN/A SERIALIZE_SCALAR(timerData); 258899SN/A SERIALIZE_SCALAR(mask1); 259899SN/A SERIALIZE_SCALAR(mask2); 260899SN/A SERIALIZE_SCALAR(mode1); 261899SN/A SERIALIZE_SCALAR(mode2); 262811SN/A SERIALIZE_SCALAR(picr); 263811SN/A SERIALIZE_SCALAR(picInterrupting); 264811SN/A 265919SN/A // Serialize the timers 2661854SN/A pitimer.serialize("pitimer", os); 2671854SN/A rtc.serialize("rtc", os); 268768SN/A} 269768SN/A 270768SN/Avoid 2711854SN/ATsunamiIO::unserialize(Checkpoint *cp, const string §ion) 272768SN/A{ 2735392Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(rtcAddr); 274811SN/A UNSERIALIZE_SCALAR(timerData); 275899SN/A UNSERIALIZE_SCALAR(mask1); 276899SN/A UNSERIALIZE_SCALAR(mask2); 277899SN/A UNSERIALIZE_SCALAR(mode1); 278899SN/A UNSERIALIZE_SCALAR(mode2); 279811SN/A UNSERIALIZE_SCALAR(picr); 280811SN/A UNSERIALIZE_SCALAR(picInterrupting); 281919SN/A 282919SN/A // Unserialize the timers 2831854SN/A pitimer.unserialize("pitimer", cp, section); 2841854SN/A rtc.unserialize("rtc", cp, section); 285768SN/A} 286768SN/A 2874762Snate@binkert.orgTsunamiIO * 2884762Snate@binkert.orgTsunamiIOParams::create() 289768SN/A{ 2904762Snate@binkert.org return new TsunamiIO(this); 291768SN/A} 292