tsunami_io.cc revision 8229
1803SN/A/* 21363SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 3803SN/A * All rights reserved. 4803SN/A * 5803SN/A * Redistribution and use in source and binary forms, with or without 6803SN/A * modification, are permitted provided that the following conditions are 7803SN/A * met: redistributions of source code must retain the above copyright 8803SN/A * notice, this list of conditions and the following disclaimer; 9803SN/A * redistributions in binary form must reproduce the above copyright 10803SN/A * notice, this list of conditions and the following disclaimer in the 11803SN/A * documentation and/or other materials provided with the distribution; 12803SN/A * neither the name of the copyright holders nor the names of its 13803SN/A * contributors may be used to endorse or promote products derived from 14803SN/A * this software without specific prior written permission. 15803SN/A * 16803SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17803SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18803SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19803SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20803SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21803SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22803SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23803SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24803SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25803SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26803SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Ali Saidi 292665SN/A * Andrew Schultz 302665SN/A * Miguel Serrano 31803SN/A */ 32768SN/A 331730SN/A/** @file 34773SN/A * Tsunami I/O including PIC, PIT, RTC, DMA 35768SN/A */ 36768SN/A 37773SN/A#include <sys/time.h> 38773SN/A 39768SN/A#include <deque> 40768SN/A#include <string> 41768SN/A#include <vector> 42768SN/A 434762Snate@binkert.org#include "base/time.hh" 44768SN/A#include "base/trace.hh" 456658Snate@binkert.org#include "config/the_isa.hh" 468229Snate@binkert.org#include "dev/alpha/tsunami.hh" 473540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_cchip.hh" 483540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_io.hh" 493540Sgblack@eecs.umich.edu#include "dev/alpha/tsunamireg.h" 508229Snate@binkert.org#include "dev/rtcreg.h" 513348SN/A#include "mem/packet.hh" 523348SN/A#include "mem/packet_access.hh" 532542SN/A#include "mem/port.hh" 542542SN/A#include "sim/system.hh" 55768SN/A 56768SN/Ausing namespace std; 572107SN/A//Should this be AlphaISA? 582107SN/Ausing namespace TheISA; 59773SN/A 605606Snate@binkert.orgTsunamiIO::RTC::RTC(const string &n, const TsunamiIOParams *p) 615606Snate@binkert.org : MC146818(p->tsunami, n, p->time, p->year_is_bcd, p->frequency), 625606Snate@binkert.org tsunami(p->tsunami) 631817SN/A{ 64772SN/A} 65772SN/A 664762Snate@binkert.orgTsunamiIO::TsunamiIO(const Params *p) 675606Snate@binkert.org : BasicPioDevice(p), tsunami(p->tsunami), 685606Snate@binkert.org pitimer(this, p->name + "pitimer"), rtc(p->name + ".rtc", p) 69768SN/A{ 703846Shsul@eecs.umich.edu pioSize = 0x100; 71909SN/A 72803SN/A // set the back pointer from tsunami to myself 73803SN/A tsunami->io = this; 74803SN/A 75771SN/A timerData = 0; 76777SN/A picr = 0; 77777SN/A picInterrupting = false; 78773SN/A} 79773SN/A 801634SN/ATick 811634SN/ATsunamiIO::frequency() const 821634SN/A{ 837064Snate@binkert.org return SimClock::Frequency / params()->frequency; 841634SN/A} 851634SN/A 862542SN/ATick 873349SN/ATsunamiIO::read(PacketPtr pkt) 88768SN/A{ 892641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 90768SN/A 912641SN/A Addr daddr = pkt->getAddr() - pioAddr; 92865SN/A 932641SN/A DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(), 942641SN/A pkt->getSize(), daddr); 95771SN/A 962630SN/A pkt->allocate(); 972539SN/A 982641SN/A if (pkt->getSize() == sizeof(uint8_t)) { 99803SN/A switch(daddr) { 1001817SN/A // PIC1 mask read 1011817SN/A case TSDEV_PIC1_MASK: 1022630SN/A pkt->set(~mask1); 1032539SN/A break; 1041817SN/A case TSDEV_PIC2_MASK: 1052630SN/A pkt->set(~mask2); 1062539SN/A break; 107865SN/A case TSDEV_PIC1_ISR: 108865SN/A // !!! If this is modified 64bit case needs to be too 109865SN/A // Pal code has to do a 64 bit physical read because there is 110865SN/A // no load physical byte instruction 1112630SN/A pkt->set(picr); 1122539SN/A break; 113865SN/A case TSDEV_PIC2_ISR: 114865SN/A // PIC2 not implemnted... just return 0 1152630SN/A pkt->set(0x00); 1162539SN/A break; 1171817SN/A case TSDEV_TMR0_DATA: 1185635Sgblack@eecs.umich.edu pkt->set(pitimer.readCounter(0)); 1192542SN/A break; 1201817SN/A case TSDEV_TMR1_DATA: 1215635Sgblack@eecs.umich.edu pkt->set(pitimer.readCounter(1)); 1222542SN/A break; 1231817SN/A case TSDEV_TMR2_DATA: 1245635Sgblack@eecs.umich.edu pkt->set(pitimer.readCounter(2)); 1252539SN/A break; 126803SN/A case TSDEV_RTC_DATA: 1275392Sgblack@eecs.umich.edu pkt->set(rtc.readData(rtcAddr)); 1282539SN/A break; 1291817SN/A case TSDEV_CTRL_PORTB: 1305635Sgblack@eecs.umich.edu if (pitimer.outputHigh(2)) 1312630SN/A pkt->set(PORTB_SPKR_HIGH); 1321817SN/A else 1332630SN/A pkt->set(0x00); 1342539SN/A break; 135803SN/A default: 1362641SN/A panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize()); 137803SN/A } 1382641SN/A } else if (pkt->getSize() == sizeof(uint64_t)) { 1392539SN/A if (daddr == TSDEV_PIC1_ISR) 1402630SN/A pkt->set<uint64_t>(picr); 1412539SN/A else 1422539SN/A panic("I/O Read - invalid addr - va %#x size %d\n", 1432641SN/A pkt->getAddr(), pkt->getSize()); 1442539SN/A } else { 1452641SN/A panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize()); 146771SN/A } 1474870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 1482539SN/A return pioDelay; 149768SN/A} 150768SN/A 1512539SN/ATick 1523349SN/ATsunamiIO::write(PacketPtr pkt) 153768SN/A{ 1542641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1552641SN/A Addr daddr = pkt->getAddr() - pioAddr; 156779SN/A 157779SN/A DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n", 1582641SN/A pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff, (uint32_t)pkt->get<uint8_t>()); 159768SN/A 1602641SN/A assert(pkt->getSize() == sizeof(uint8_t)); 161769SN/A 1622539SN/A switch(daddr) { 1632539SN/A case TSDEV_PIC1_MASK: 1642630SN/A mask1 = ~(pkt->get<uint8_t>()); 1652539SN/A if ((picr & mask1) && !picInterrupting) { 1662539SN/A picInterrupting = true; 1672539SN/A tsunami->cchip->postDRIR(55); 1682539SN/A DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); 169803SN/A } 1702539SN/A if ((!(picr & mask1)) && picInterrupting) { 1712539SN/A picInterrupting = false; 1722539SN/A tsunami->cchip->clearDRIR(55); 1732539SN/A DPRINTF(Tsunami, "clearing pic interrupt\n"); 1742539SN/A } 1752539SN/A break; 1762539SN/A case TSDEV_PIC2_MASK: 1772630SN/A mask2 = pkt->get<uint8_t>(); 1782539SN/A //PIC2 Not implemented to interrupt 1792539SN/A break; 1802539SN/A case TSDEV_PIC1_ACK: 1812539SN/A // clear the interrupt on the PIC 1822630SN/A picr &= ~(1 << (pkt->get<uint8_t>() & 0xF)); 1832539SN/A if (!(picr & mask1)) 1842539SN/A tsunami->cchip->clearDRIR(55); 1852539SN/A break; 1862539SN/A case TSDEV_DMA1_MODE: 1872630SN/A mode1 = pkt->get<uint8_t>(); 1882539SN/A break; 1892539SN/A case TSDEV_DMA2_MODE: 1902630SN/A mode2 = pkt->get<uint8_t>(); 1912539SN/A break; 1922539SN/A case TSDEV_TMR0_DATA: 1935635Sgblack@eecs.umich.edu pitimer.writeCounter(0, pkt->get<uint8_t>()); 1942539SN/A break; 1952539SN/A case TSDEV_TMR1_DATA: 1965635Sgblack@eecs.umich.edu pitimer.writeCounter(1, pkt->get<uint8_t>()); 1972539SN/A break; 1982539SN/A case TSDEV_TMR2_DATA: 1995635Sgblack@eecs.umich.edu pitimer.writeCounter(2, pkt->get<uint8_t>()); 2002539SN/A break; 2012539SN/A case TSDEV_TMR_CTRL: 2022630SN/A pitimer.writeControl(pkt->get<uint8_t>()); 2032539SN/A break; 2042539SN/A case TSDEV_RTC_ADDR: 2055392Sgblack@eecs.umich.edu rtcAddr = pkt->get<uint8_t>(); 2062539SN/A break; 2072539SN/A case TSDEV_RTC_DATA: 2085392Sgblack@eecs.umich.edu rtc.writeData(rtcAddr, pkt->get<uint8_t>()); 2092539SN/A break; 2102539SN/A case TSDEV_KBD: 2112539SN/A case TSDEV_DMA1_CMND: 2122539SN/A case TSDEV_DMA2_CMND: 2132539SN/A case TSDEV_DMA1_MMASK: 2142539SN/A case TSDEV_DMA2_MMASK: 2152539SN/A case TSDEV_PIC2_ACK: 2162539SN/A case TSDEV_DMA1_RESET: 2172539SN/A case TSDEV_DMA2_RESET: 2182539SN/A case TSDEV_DMA1_MASK: 2192539SN/A case TSDEV_DMA2_MASK: 2202539SN/A case TSDEV_CTRL_PORTB: 2212539SN/A break; 222803SN/A default: 2232641SN/A panic("I/O Write - va%#x size %d data %#x\n", pkt->getAddr(), pkt->getSize(), pkt->get<uint8_t>()); 224769SN/A } 225769SN/A 2264870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 2272539SN/A return pioDelay; 228768SN/A} 229768SN/A 230768SN/Avoid 231777SN/ATsunamiIO::postPIC(uint8_t bitvector) 232777SN/A{ 233777SN/A //PIC2 Is not implemented, because nothing of interest there 234777SN/A picr |= bitvector; 235865SN/A if (picr & mask1) { 236817SN/A tsunami->cchip->postDRIR(55); 237777SN/A DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); 238777SN/A } 239777SN/A} 240777SN/A 241777SN/Avoid 242777SN/ATsunamiIO::clearPIC(uint8_t bitvector) 243777SN/A{ 244777SN/A //PIC2 Is not implemented, because nothing of interest there 245777SN/A picr &= ~bitvector; 246777SN/A if (!(picr & mask1)) { 247817SN/A tsunami->cchip->clearDRIR(55); 248777SN/A DPRINTF(Tsunami, "clearing pic interrupt to cchip\n"); 249777SN/A } 250777SN/A} 251777SN/A 252777SN/Avoid 2531854SN/ATsunamiIO::serialize(ostream &os) 254768SN/A{ 2555392Sgblack@eecs.umich.edu SERIALIZE_SCALAR(rtcAddr); 256811SN/A SERIALIZE_SCALAR(timerData); 257899SN/A SERIALIZE_SCALAR(mask1); 258899SN/A SERIALIZE_SCALAR(mask2); 259899SN/A SERIALIZE_SCALAR(mode1); 260899SN/A SERIALIZE_SCALAR(mode2); 261811SN/A SERIALIZE_SCALAR(picr); 262811SN/A SERIALIZE_SCALAR(picInterrupting); 263811SN/A 264919SN/A // Serialize the timers 2651854SN/A pitimer.serialize("pitimer", os); 2661854SN/A rtc.serialize("rtc", os); 267768SN/A} 268768SN/A 269768SN/Avoid 2701854SN/ATsunamiIO::unserialize(Checkpoint *cp, const string §ion) 271768SN/A{ 2725392Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(rtcAddr); 273811SN/A UNSERIALIZE_SCALAR(timerData); 274899SN/A UNSERIALIZE_SCALAR(mask1); 275899SN/A UNSERIALIZE_SCALAR(mask2); 276899SN/A UNSERIALIZE_SCALAR(mode1); 277899SN/A UNSERIALIZE_SCALAR(mode2); 278811SN/A UNSERIALIZE_SCALAR(picr); 279811SN/A UNSERIALIZE_SCALAR(picInterrupting); 280919SN/A 281919SN/A // Unserialize the timers 2821854SN/A pitimer.unserialize("pitimer", cp, section); 2831854SN/A rtc.unserialize("rtc", cp, section); 284768SN/A} 285768SN/A 2864762Snate@binkert.orgTsunamiIO * 2874762Snate@binkert.orgTsunamiIOParams::create() 288768SN/A{ 2894762Snate@binkert.org return new TsunamiIO(this); 290768SN/A} 291