tsunami_io.cc revision 817
112391Sjason@lowepower.com/* 212391Sjason@lowepower.com * Copyright (c) 2003 The Regents of The University of Michigan 312391Sjason@lowepower.com * All rights reserved. 412391Sjason@lowepower.com * 512391Sjason@lowepower.com * Redistribution and use in source and binary forms, with or without 612391Sjason@lowepower.com * modification, are permitted provided that the following conditions are 712391Sjason@lowepower.com * met: redistributions of source code must retain the above copyright 812391Sjason@lowepower.com * notice, this list of conditions and the following disclaimer; 912391Sjason@lowepower.com * redistributions in binary form must reproduce the above copyright 1012391Sjason@lowepower.com * notice, this list of conditions and the following disclaimer in the 1112391Sjason@lowepower.com * documentation and/or other materials provided with the distribution; 1212391Sjason@lowepower.com * neither the name of the copyright holders nor the names of its 1312391Sjason@lowepower.com * contributors may be used to endorse or promote products derived from 1412391Sjason@lowepower.com * this software without specific prior written permission. 1512391Sjason@lowepower.com * 1612391Sjason@lowepower.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712391Sjason@lowepower.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812391Sjason@lowepower.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912391Sjason@lowepower.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012391Sjason@lowepower.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112391Sjason@lowepower.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212391Sjason@lowepower.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312391Sjason@lowepower.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412391Sjason@lowepower.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512391Sjason@lowepower.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612391Sjason@lowepower.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712391Sjason@lowepower.com */ 2812391Sjason@lowepower.com 2912391Sjason@lowepower.com/* @file 3014299Sbbruce@ucdavis.edu * Tsunami I/O including PIC, PIT, RTC, DMA 3112391Sjason@lowepower.com */ 3212391Sjason@lowepower.com 3314299Sbbruce@ucdavis.edu#include <sys/time.h> 3412391Sjason@lowepower.com 3512391Sjason@lowepower.com#include <deque> 3612391Sjason@lowepower.com#include <string> 3714299Sbbruce@ucdavis.edu#include <vector> 3812391Sjason@lowepower.com 3914299Sbbruce@ucdavis.edu#include "base/trace.hh" 4012391Sjason@lowepower.com#include "cpu/exec_context.hh" 4112391Sjason@lowepower.com#include "dev/console.hh" 4212391Sjason@lowepower.com#include "dev/tlaser_clock.hh" 4312391Sjason@lowepower.com#include "dev/tsunami_io.hh" 4412391Sjason@lowepower.com#include "dev/tsunamireg.h" 4512391Sjason@lowepower.com#include "dev/tsunami.hh" 4612391Sjason@lowepower.com#include "mem/functional_mem/memory_control.hh" 4712391Sjason@lowepower.com#include "sim/builder.hh" 4812391Sjason@lowepower.com#include "dev/tsunami_cchip.hh" 4912391Sjason@lowepower.com 5014299Sbbruce@ucdavis.eduusing namespace std; 5114299Sbbruce@ucdavis.edu 5212391Sjason@lowepower.com#define UNIX_YEAR_OFFSET 52 5312391Sjason@lowepower.com 5412391Sjason@lowepower.com// Timer Event for Periodic interrupt of RTC 5512391Sjason@lowepower.comTsunamiIO::RTCEvent::RTCEvent(Tsunami* t) 5612391Sjason@lowepower.com : Event(&mainEventQueue), tsunami(t) 5712391Sjason@lowepower.com{ 5812391Sjason@lowepower.com DPRINTF(MC146818, "RTC Event Initilizing\n"); 5912391Sjason@lowepower.com schedule(curTick + ticksPerSecond/RTC_RATE); 6012391Sjason@lowepower.com} 6112391Sjason@lowepower.com 6212391Sjason@lowepower.comvoid 6312391Sjason@lowepower.comTsunamiIO::RTCEvent::process() 6412391Sjason@lowepower.com{ 6512391Sjason@lowepower.com DPRINTF(MC146818, "RTC Timer Interrupt\n"); 6612391Sjason@lowepower.com schedule(curTick + ticksPerSecond/RTC_RATE); 6712391Sjason@lowepower.com //Actually interrupt the processor here 6812391Sjason@lowepower.com if (!tsunami->cchip->RTCInterrupting) { 6912391Sjason@lowepower.com tsunami->cchip->misc |= 1 << 7; 7012391Sjason@lowepower.com tsunami->cchip->RTCInterrupting = true; 7112391Sjason@lowepower.com tsunami->intrctrl->post(0, TheISA::INTLEVEL_IRQ2, 0); 7212391Sjason@lowepower.com } 7312391Sjason@lowepower.com} 7412391Sjason@lowepower.com 7512391Sjason@lowepower.comconst char * 7612391Sjason@lowepower.comTsunamiIO::RTCEvent::description() 7712391Sjason@lowepower.com{ 7812391Sjason@lowepower.com return "tsunami RTC 1024Hz interrupt"; 7912391Sjason@lowepower.com} 8012391Sjason@lowepower.com 8112391Sjason@lowepower.com// Timer Event for PIT Timers 8212391Sjason@lowepower.comTsunamiIO::ClockEvent::ClockEvent() 8312391Sjason@lowepower.com : Event(&mainEventQueue) 8412391Sjason@lowepower.com{ 8512391Sjason@lowepower.com DPRINTF(Tsunami, "Clock Event Initilizing\n"); 8612391Sjason@lowepower.com mode = 0; 8712391Sjason@lowepower.com} 8812391Sjason@lowepower.com 8912391Sjason@lowepower.comvoid 9012391Sjason@lowepower.comTsunamiIO::ClockEvent::process() 9112391Sjason@lowepower.com{ 9212391Sjason@lowepower.com DPRINTF(Tsunami, "Timer Interrupt\n"); 9312391Sjason@lowepower.com if (mode == 0) 9412391Sjason@lowepower.com status = 0x20; // set bit that linux is looking for 9512391Sjason@lowepower.com else 9614299Sbbruce@ucdavis.edu schedule(curTick + interval); 9712391Sjason@lowepower.com} 9812391Sjason@lowepower.com 9912391Sjason@lowepower.comvoid 10012391Sjason@lowepower.comTsunamiIO::ClockEvent::Program(int count) 10112391Sjason@lowepower.com{ 10212391Sjason@lowepower.com DPRINTF(Tsunami, "Timer set to curTick + %d\n", count); 10312391Sjason@lowepower.com // should be count * (cpufreq/pitfreq) 10412391Sjason@lowepower.com interval = count * ticksPerSecond/1193180UL; 10512391Sjason@lowepower.com schedule(curTick + interval); 10612391Sjason@lowepower.com status = 0; 10712391Sjason@lowepower.com} 10812391Sjason@lowepower.com 10912391Sjason@lowepower.comconst char * 11012391Sjason@lowepower.comTsunamiIO::ClockEvent::description() 11112391Sjason@lowepower.com{ 11212391Sjason@lowepower.com return "tsunami 8254 Interval timer"; 11312391Sjason@lowepower.com} 11412391Sjason@lowepower.com 11512391Sjason@lowepower.comvoid 11612391Sjason@lowepower.comTsunamiIO::ClockEvent::ChangeMode(uint8_t md) 11712391Sjason@lowepower.com{ 11812391Sjason@lowepower.com mode = md; 11912391Sjason@lowepower.com} 12012391Sjason@lowepower.com 12112391Sjason@lowepower.comuint8_t 12212391Sjason@lowepower.comTsunamiIO::ClockEvent::Status() 12312391Sjason@lowepower.com{ 12412391Sjason@lowepower.com return status; 12512391Sjason@lowepower.com} 12612391Sjason@lowepower.com 12712391Sjason@lowepower.comTsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time, 12812391Sjason@lowepower.com Addr a, MemoryController *mmu) 12912391Sjason@lowepower.com : FunctionalMemory(name), addr(a), tsunami(t), rtc(t) 13012391Sjason@lowepower.com{ 13112391Sjason@lowepower.com mmu->add_child(this, Range<Addr>(addr, addr + size)); 13212391Sjason@lowepower.com 13312391Sjason@lowepower.com // set the back pointer from tsunami to myself 13412391Sjason@lowepower.com tsunami->io = this; 13512391Sjason@lowepower.com 13612391Sjason@lowepower.com timerData = 0; 13712391Sjason@lowepower.com set_time(init_time == 0 ? time(NULL) : init_time); 13812391Sjason@lowepower.com uip = 1; 13912391Sjason@lowepower.com picr = 0; 14012391Sjason@lowepower.com picInterrupting = false; 14112391Sjason@lowepower.com} 14212391Sjason@lowepower.com 14312391Sjason@lowepower.comvoid 14412391Sjason@lowepower.comTsunamiIO::set_time(time_t t) 14512391Sjason@lowepower.com{ 14612391Sjason@lowepower.com gmtime_r(&t, &tm); 14712391Sjason@lowepower.com DPRINTFN("Real-time clock set to %s", asctime(&tm)); 14812391Sjason@lowepower.com} 14912391Sjason@lowepower.com 15012391Sjason@lowepower.comFault 15112391Sjason@lowepower.comTsunamiIO::read(MemReqPtr &req, uint8_t *data) 15212391Sjason@lowepower.com{ 15312391Sjason@lowepower.com DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", 15412391Sjason@lowepower.com req->vaddr, req->size, req->vaddr & 0xfff); 15512391Sjason@lowepower.com 15612391Sjason@lowepower.com Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)); 15712391Sjason@lowepower.com// ExecContext *xc = req->xc; 15814299Sbbruce@ucdavis.edu// int cpuid = xc->cpu_id; 15914299Sbbruce@ucdavis.edu 16012391Sjason@lowepower.com switch(req->size) { 16112391Sjason@lowepower.com case sizeof(uint8_t): 16212391Sjason@lowepower.com switch(daddr) { 16312391Sjason@lowepower.com case TSDEV_TMR_CTL: 16412391Sjason@lowepower.com *(uint8_t*)data = timer2.Status(); 16512391Sjason@lowepower.com return No_Fault; 16612391Sjason@lowepower.com case TSDEV_RTC_DATA: 16714299Sbbruce@ucdavis.edu switch(RTCAddress) { 16812391Sjason@lowepower.com case RTC_CONTROL_REGISTERA: 16914299Sbbruce@ucdavis.edu *(uint8_t*)data = uip << 7 | 0x26; 17012391Sjason@lowepower.com uip = !uip; 17112391Sjason@lowepower.com return No_Fault; 17212391Sjason@lowepower.com case RTC_CONTROL_REGISTERB: 17312391Sjason@lowepower.com // DM and 24/12 and UIE 17412391Sjason@lowepower.com *(uint8_t*)data = 0x46; 17512391Sjason@lowepower.com return No_Fault; 17612391Sjason@lowepower.com case RTC_CONTROL_REGISTERC: 17712391Sjason@lowepower.com // If we want to support RTC user access in linux 17812391Sjason@lowepower.com // This won't work, but for now it's fine 17912391Sjason@lowepower.com *(uint8_t*)data = 0x00; 18012391Sjason@lowepower.com return No_Fault; 18112391Sjason@lowepower.com case RTC_CONTROL_REGISTERD: 18212391Sjason@lowepower.com panic("RTC Control Register D not implemented"); 18312391Sjason@lowepower.com case RTC_SECOND: 18414299Sbbruce@ucdavis.edu *(uint8_t *)data = tm.tm_sec; 18514299Sbbruce@ucdavis.edu return No_Fault; 18612391Sjason@lowepower.com case RTC_MINUTE: 18712391Sjason@lowepower.com *(uint8_t *)data = tm.tm_min; 18812391Sjason@lowepower.com return No_Fault; 18912391Sjason@lowepower.com case RTC_HOUR: 19012391Sjason@lowepower.com *(uint8_t *)data = tm.tm_hour; 19112391Sjason@lowepower.com return No_Fault; 19212391Sjason@lowepower.com case RTC_DAY_OF_WEEK: 19314299Sbbruce@ucdavis.edu *(uint8_t *)data = tm.tm_wday; 19412391Sjason@lowepower.com return No_Fault; 19512391Sjason@lowepower.com case RTC_DAY_OF_MONTH: 19614299Sbbruce@ucdavis.edu *(uint8_t *)data = tm.tm_mday; 19712391Sjason@lowepower.com case RTC_MONTH: 19812391Sjason@lowepower.com *(uint8_t *)data = tm.tm_mon + 1; 19912391Sjason@lowepower.com return No_Fault; 20012391Sjason@lowepower.com case RTC_YEAR: 20112391Sjason@lowepower.com *(uint8_t *)data = tm.tm_year - UNIX_YEAR_OFFSET; 20212391Sjason@lowepower.com return No_Fault; 20312391Sjason@lowepower.com default: 20412391Sjason@lowepower.com panic("Unknown RTC Address\n"); 20512391Sjason@lowepower.com } 20612391Sjason@lowepower.com 20712391Sjason@lowepower.com default: 20812391Sjason@lowepower.com panic("I/O Read - va%#x size %d\n", req->vaddr, req->size); 20912391Sjason@lowepower.com } 21012391Sjason@lowepower.com case sizeof(uint16_t): 21112391Sjason@lowepower.com case sizeof(uint32_t): 21212391Sjason@lowepower.com case sizeof(uint64_t): 21312391Sjason@lowepower.com default: 21412391Sjason@lowepower.com panic("I/O Read - invalid size - va %#x size %d\n", 21514299Sbbruce@ucdavis.edu req->vaddr, req->size); 21614299Sbbruce@ucdavis.edu } 21714299Sbbruce@ucdavis.edu panic("I/O Read - va%#x size %d\n", req->vaddr, req->size); 21814299Sbbruce@ucdavis.edu 21914299Sbbruce@ucdavis.edu return No_Fault; 22014299Sbbruce@ucdavis.edu} 22114299Sbbruce@ucdavis.edu 22214299Sbbruce@ucdavis.eduFault 22314299Sbbruce@ucdavis.eduTsunamiIO::write(MemReqPtr &req, const uint8_t *data) 22414299Sbbruce@ucdavis.edu{ 22514299Sbbruce@ucdavis.edu uint8_t dt = *(uint8_t*)data; 22614299Sbbruce@ucdavis.edu uint64_t dt64 = dt; 22714299Sbbruce@ucdavis.edu 22814299Sbbruce@ucdavis.edu DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n", 22914299Sbbruce@ucdavis.edu req->vaddr, req->size, req->vaddr & 0xfff, dt64); 23014299Sbbruce@ucdavis.edu 23114299Sbbruce@ucdavis.edu Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)); 23214299Sbbruce@ucdavis.edu 23314299Sbbruce@ucdavis.edu switch(req->size) { 23414299Sbbruce@ucdavis.edu case sizeof(uint8_t): 23514299Sbbruce@ucdavis.edu switch(daddr) { 23614299Sbbruce@ucdavis.edu case TSDEV_PIC1_MASK: 23714299Sbbruce@ucdavis.edu mask1 = *(uint8_t*)data; 23814299Sbbruce@ucdavis.edu if ((picr & mask1) && !picInterrupting) { 23914299Sbbruce@ucdavis.edu picInterrupting = true; 24012391Sjason@lowepower.com tsunami->cchip->postDRIR(55); 24112391Sjason@lowepower.com DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); 24212391Sjason@lowepower.com } 24312391Sjason@lowepower.com return No_Fault; 24412391Sjason@lowepower.com case TSDEV_PIC2_MASK: 24512391Sjason@lowepower.com mask2 = *(uint8_t*)data; 24612391Sjason@lowepower.com //PIC2 Not implemented to interrupt 24712391Sjason@lowepower.com return No_Fault; 24812391Sjason@lowepower.com case TSDEV_DMA1_RESET: 24912391Sjason@lowepower.com return No_Fault; 25012391Sjason@lowepower.com case TSDEV_DMA2_RESET: 25112391Sjason@lowepower.com return No_Fault; 25212391Sjason@lowepower.com case TSDEV_DMA1_MODE: 25312391Sjason@lowepower.com mode1 = *(uint8_t*)data; 25412391Sjason@lowepower.com return No_Fault; 25512391Sjason@lowepower.com case TSDEV_DMA2_MODE: 25612391Sjason@lowepower.com mode2 = *(uint8_t*)data; 25712391Sjason@lowepower.com return No_Fault; 25812391Sjason@lowepower.com case TSDEV_DMA1_MASK: 25914299Sbbruce@ucdavis.edu case TSDEV_DMA2_MASK: 26012391Sjason@lowepower.com return No_Fault; 26112391Sjason@lowepower.com case TSDEV_TMR_CTL: 26214299Sbbruce@ucdavis.edu return No_Fault; 26312391Sjason@lowepower.com case TSDEV_TMR2_CTL: 26412391Sjason@lowepower.com if ((*(uint8_t*)data & 0x30) != 0x30) 26512391Sjason@lowepower.com panic("Only L/M write supported\n"); 26612391Sjason@lowepower.com 26712391Sjason@lowepower.com switch(*(uint8_t*)data >> 6) { 26812391Sjason@lowepower.com case 0: 26912391Sjason@lowepower.com timer0.ChangeMode((*(uint8_t*)data & 0xF) >> 1); 27012391Sjason@lowepower.com break; 27112391Sjason@lowepower.com case 2: 27212391Sjason@lowepower.com timer2.ChangeMode((*(uint8_t*)data & 0xF) >> 1); 27312391Sjason@lowepower.com break; 27412391Sjason@lowepower.com default: 27512391Sjason@lowepower.com panic("Read Back Command not implemented\n"); 27612391Sjason@lowepower.com } 27712391Sjason@lowepower.com return No_Fault; 27812391Sjason@lowepower.com case TSDEV_TMR2_DATA: 27912391Sjason@lowepower.com /* two writes before we actually start the Timer 28012391Sjason@lowepower.com so I set a flag in the timerData */ 28112391Sjason@lowepower.com if(timerData & 0x1000) { 28212391Sjason@lowepower.com timerData &= 0x1000; 28312391Sjason@lowepower.com timerData += *(uint8_t*)data << 8; 28412391Sjason@lowepower.com timer2.Program(timerData); 28512391Sjason@lowepower.com } else { 28614299Sbbruce@ucdavis.edu timerData = *(uint8_t*)data; 28712391Sjason@lowepower.com timerData |= 0x1000; 28812391Sjason@lowepower.com } 28912391Sjason@lowepower.com return No_Fault; 29012391Sjason@lowepower.com case TSDEV_TMR0_DATA: 29114299Sbbruce@ucdavis.edu /* two writes before we actually start the Timer 29212391Sjason@lowepower.com so I set a flag in the timerData */ 29312391Sjason@lowepower.com if(timerData & 0x1000) { 29412391Sjason@lowepower.com timerData &= 0x1000; 29512391Sjason@lowepower.com timerData += *(uint8_t*)data << 8; 29612391Sjason@lowepower.com timer0.Program(timerData); 29712391Sjason@lowepower.com } else { 29812391Sjason@lowepower.com timerData = *(uint8_t*)data; 29912391Sjason@lowepower.com timerData |= 0x1000; 30012391Sjason@lowepower.com } 30112391Sjason@lowepower.com return No_Fault; 30212391Sjason@lowepower.com case TSDEV_RTC_ADDR: 30312391Sjason@lowepower.com RTCAddress = *(uint8_t*)data; 30412391Sjason@lowepower.com return No_Fault; 30512391Sjason@lowepower.com case TSDEV_RTC_DATA: 30612391Sjason@lowepower.com panic("RTC Write not implmented (rtc.o won't work)\n"); 30712391Sjason@lowepower.com default: 30812391Sjason@lowepower.com panic("I/O Write - va%#x size %d\n", req->vaddr, req->size); 30912391Sjason@lowepower.com } 31012391Sjason@lowepower.com case sizeof(uint16_t): 31112391Sjason@lowepower.com case sizeof(uint32_t): 31212391Sjason@lowepower.com case sizeof(uint64_t): 31312391Sjason@lowepower.com default: 31412391Sjason@lowepower.com panic("I/O Write - invalid size - va %#x size %d\n", 31512391Sjason@lowepower.com req->vaddr, req->size); 31612391Sjason@lowepower.com } 31712391Sjason@lowepower.com 31812391Sjason@lowepower.com 31912391Sjason@lowepower.com return No_Fault; 32012391Sjason@lowepower.com} 32112391Sjason@lowepower.com 32212391Sjason@lowepower.comvoid 32312391Sjason@lowepower.comTsunamiIO::postPIC(uint8_t bitvector) 32412391Sjason@lowepower.com{ 32512391Sjason@lowepower.com //PIC2 Is not implemented, because nothing of interest there 32612391Sjason@lowepower.com picr |= bitvector; 32712391Sjason@lowepower.com if ((picr & mask1) && !picInterrupting) { 32812391Sjason@lowepower.com picInterrupting = true; 32912391Sjason@lowepower.com tsunami->cchip->postDRIR(55); 33012391Sjason@lowepower.com DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); 33112391Sjason@lowepower.com } 33212391Sjason@lowepower.com} 33312391Sjason@lowepower.com 33412391Sjason@lowepower.comvoid 33512391Sjason@lowepower.comTsunamiIO::clearPIC(uint8_t bitvector) 33612391Sjason@lowepower.com{ 33712391Sjason@lowepower.com //PIC2 Is not implemented, because nothing of interest there 33812391Sjason@lowepower.com picr &= ~bitvector; 33912391Sjason@lowepower.com if (!(picr & mask1)) { 34012391Sjason@lowepower.com picInterrupting = false; 34112391Sjason@lowepower.com tsunami->cchip->clearDRIR(55); 34212391Sjason@lowepower.com DPRINTF(Tsunami, "clearing pic interrupt to cchip\n"); 34312391Sjason@lowepower.com } 34412391Sjason@lowepower.com} 34512391Sjason@lowepower.com 34612391Sjason@lowepower.comvoid 34712391Sjason@lowepower.comTsunamiIO::serialize(std::ostream &os) 34812391Sjason@lowepower.com{ 34912391Sjason@lowepower.com SERIALIZE_SCALAR(timerData); 35012391Sjason@lowepower.com SERIALIZE_SCALAR(uip); 35112391Sjason@lowepower.com SERIALIZE_SCALAR(picr); 35212391Sjason@lowepower.com SERIALIZE_SCALAR(picInterrupting); 35312391Sjason@lowepower.com Tick time0when = timer0.when(); 35412391Sjason@lowepower.com Tick time2when = timer2.when(); 35512391Sjason@lowepower.com Tick rtcwhen = rtc.when(); 35612391Sjason@lowepower.com SERIALIZE_SCALAR(time0when); 35712391Sjason@lowepower.com SERIALIZE_SCALAR(time2when); 35812391Sjason@lowepower.com SERIALIZE_SCALAR(rtcwhen); 35912391Sjason@lowepower.com 36012391Sjason@lowepower.com} 36112391Sjason@lowepower.com 36212391Sjason@lowepower.comvoid 36312391Sjason@lowepower.comTsunamiIO::unserialize(Checkpoint *cp, const std::string §ion) 36412391Sjason@lowepower.com{ 36512391Sjason@lowepower.com UNSERIALIZE_SCALAR(timerData); 36612391Sjason@lowepower.com UNSERIALIZE_SCALAR(uip); 36712391Sjason@lowepower.com UNSERIALIZE_SCALAR(picr); 36812391Sjason@lowepower.com UNSERIALIZE_SCALAR(picInterrupting); 36912391Sjason@lowepower.com Tick time0when; 37012391Sjason@lowepower.com Tick time2when; 37112391Sjason@lowepower.com Tick rtcwhen; 37212391Sjason@lowepower.com UNSERIALIZE_SCALAR(time0when); 37312391Sjason@lowepower.com UNSERIALIZE_SCALAR(time2when); 37412391Sjason@lowepower.com UNSERIALIZE_SCALAR(rtcwhen); 37512391Sjason@lowepower.com timer0.reschedule(time0when); 37614299Sbbruce@ucdavis.edu timer2.reschedule(time2when); 37714299Sbbruce@ucdavis.edu rtc.reschedule(rtcwhen); 37814299Sbbruce@ucdavis.edu} 37914299Sbbruce@ucdavis.edu 38014299Sbbruce@ucdavis.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO) 38112391Sjason@lowepower.com 38212391Sjason@lowepower.com SimObjectParam<Tsunami *> tsunami; 38312391Sjason@lowepower.com Param<time_t> time; 38412391Sjason@lowepower.com SimObjectParam<MemoryController *> mmu; 38512391Sjason@lowepower.com Param<Addr> addr; 38612391Sjason@lowepower.com 38714299Sbbruce@ucdavis.eduEND_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO) 38812391Sjason@lowepower.com 38914299Sbbruce@ucdavis.eduBEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO) 39012391Sjason@lowepower.com 39112391Sjason@lowepower.com INIT_PARAM(tsunami, "Tsunami"), 39212391Sjason@lowepower.com INIT_PARAM_DFLT(time, "System time to use " 39312391Sjason@lowepower.com "(0 for actual time, default is 1/1/06", ULL(1136073600)), 39412391Sjason@lowepower.com INIT_PARAM(mmu, "Memory Controller"), 39512391Sjason@lowepower.com INIT_PARAM(addr, "Device Address") 39612391Sjason@lowepower.com 39712391Sjason@lowepower.comEND_INIT_SIM_OBJECT_PARAMS(TsunamiIO) 39812391Sjason@lowepower.com 39912391Sjason@lowepower.comCREATE_SIM_OBJECT(TsunamiIO) 40012391Sjason@lowepower.com{ 40112391Sjason@lowepower.com return new TsunamiIO(getInstanceName(), tsunami, time, addr, mmu); 40212391Sjason@lowepower.com} 40312391Sjason@lowepower.com 40412391Sjason@lowepower.comREGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO) 40512391Sjason@lowepower.com