tsunami_io.cc revision 6658
12623SN/A/*
22623SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
32623SN/A * All rights reserved.
42623SN/A *
52623SN/A * Redistribution and use in source and binary forms, with or without
62623SN/A * modification, are permitted provided that the following conditions are
72623SN/A * met: redistributions of source code must retain the above copyright
82623SN/A * notice, this list of conditions and the following disclaimer;
92623SN/A * redistributions in binary form must reproduce the above copyright
102623SN/A * notice, this list of conditions and the following disclaimer in the
112623SN/A * documentation and/or other materials provided with the distribution;
122623SN/A * neither the name of the copyright holders nor the names of its
132623SN/A * contributors may be used to endorse or promote products derived from
142623SN/A * this software without specific prior written permission.
152623SN/A *
162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Ali Saidi
292623SN/A *          Andrew Schultz
302623SN/A *          Miguel Serrano
312623SN/A */
322623SN/A
332623SN/A/** @file
342623SN/A * Tsunami I/O including PIC, PIT, RTC, DMA
352623SN/A */
362623SN/A
372623SN/A#include <sys/time.h>
382623SN/A
392623SN/A#include <deque>
402623SN/A#include <string>
412623SN/A#include <vector>
422623SN/A
432623SN/A#include "base/time.hh"
442623SN/A#include "base/trace.hh"
452623SN/A#include "config/the_isa.hh"
462623SN/A#include "dev/rtcreg.h"
472623SN/A#include "dev/alpha/tsunami_cchip.hh"
482623SN/A#include "dev/alpha/tsunami.hh"
492623SN/A#include "dev/alpha/tsunami_io.hh"
502623SN/A#include "dev/alpha/tsunamireg.h"
512623SN/A#include "mem/packet.hh"
522623SN/A#include "mem/packet_access.hh"
532623SN/A#include "mem/port.hh"
542623SN/A#include "sim/system.hh"
552623SN/A
562623SN/Ausing namespace std;
572623SN/A//Should this be AlphaISA?
582623SN/Ausing namespace TheISA;
592623SN/A
602623SN/ATsunamiIO::RTC::RTC(const string &n, const TsunamiIOParams *p)
612623SN/A    : MC146818(p->tsunami, n, p->time, p->year_is_bcd, p->frequency),
622623SN/A      tsunami(p->tsunami)
632623SN/A{
642623SN/A}
652623SN/A
662623SN/ATsunamiIO::TsunamiIO(const Params *p)
672623SN/A    : BasicPioDevice(p), tsunami(p->tsunami),
682623SN/A      pitimer(this, p->name + "pitimer"), rtc(p->name + ".rtc", p)
692623SN/A{
702623SN/A    pioSize = 0x100;
712623SN/A
722623SN/A    // set the back pointer from tsunami to myself
732623SN/A    tsunami->io = this;
742623SN/A
752623SN/A    timerData = 0;
762623SN/A    picr = 0;
772623SN/A    picInterrupting = false;
782623SN/A}
792623SN/A
802623SN/ATick
812623SN/ATsunamiIO::frequency() const
822623SN/A{
832623SN/A    return Clock::Frequency / params()->frequency;
842623SN/A}
852623SN/A
862623SN/ATick
872623SN/ATsunamiIO::read(PacketPtr pkt)
882623SN/A{
892640Sstever@eecs.umich.edu    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
902640Sstever@eecs.umich.edu
912623SN/A    Addr daddr = pkt->getAddr() - pioAddr;
922623SN/A
932623SN/A    DPRINTF(Tsunami, "io read  va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(),
942623SN/A            pkt->getSize(), daddr);
952630SN/A
962623SN/A    pkt->allocate();
972630SN/A
982623SN/A    if (pkt->getSize() == sizeof(uint8_t)) {
992630SN/A        switch(daddr) {
1002623SN/A          // PIC1 mask read
1012623SN/A          case TSDEV_PIC1_MASK:
1022623SN/A            pkt->set(~mask1);
1032657Ssaidi@eecs.umich.edu            break;
1042623SN/A          case TSDEV_PIC2_MASK:
1052623SN/A            pkt->set(~mask2);
1062623SN/A            break;
1073192Srdreslin@umich.edu          case TSDEV_PIC1_ISR:
1083192Srdreslin@umich.edu              // !!! If this is modified 64bit case needs to be too
1092623SN/A              // Pal code has to do a 64 bit physical read because there is
1102623SN/A              // no load physical byte instruction
1112623SN/A              pkt->set(picr);
1122623SN/A              break;
1132623SN/A          case TSDEV_PIC2_ISR:
1142623SN/A              // PIC2 not implemnted... just return 0
1152623SN/A              pkt->set(0x00);
1162623SN/A              break;
1172623SN/A          case TSDEV_TMR0_DATA:
1182623SN/A            pkt->set(pitimer.readCounter(0));
1192623SN/A            break;
1202623SN/A          case TSDEV_TMR1_DATA:
1212662Sstever@eecs.umich.edu            pkt->set(pitimer.readCounter(1));
1222623SN/A            break;
1232623SN/A          case TSDEV_TMR2_DATA:
1242623SN/A            pkt->set(pitimer.readCounter(2));
1252856Srdreslin@umich.edu            break;
1262856Srdreslin@umich.edu          case TSDEV_RTC_DATA:
1272623SN/A            pkt->set(rtc.readData(rtcAddr));
1282623SN/A            break;
1292915Sktlim@umich.edu          case TSDEV_CTRL_PORTB:
1302623SN/A            if (pitimer.outputHigh(2))
1312798Sktlim@umich.edu                pkt->set(PORTB_SPKR_HIGH);
1322623SN/A            else
1332623SN/A                pkt->set(0x00);
1342623SN/A            break;
1352623SN/A          default:
1362623SN/A            panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize());
1372623SN/A        }
1382623SN/A    } else if (pkt->getSize() == sizeof(uint64_t)) {
1392623SN/A        if (daddr == TSDEV_PIC1_ISR)
1402623SN/A            pkt->set<uint64_t>(picr);
1412623SN/A        else
1422623SN/A           panic("I/O Read - invalid addr - va %#x size %d\n",
1432623SN/A                   pkt->getAddr(), pkt->getSize());
1442623SN/A    } else {
145       panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize());
146    }
147    pkt->makeAtomicResponse();
148    return pioDelay;
149}
150
151Tick
152TsunamiIO::write(PacketPtr pkt)
153{
154    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
155    Addr daddr = pkt->getAddr() - pioAddr;
156
157    DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
158            pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff, (uint32_t)pkt->get<uint8_t>());
159
160    assert(pkt->getSize() == sizeof(uint8_t));
161
162    switch(daddr) {
163      case TSDEV_PIC1_MASK:
164        mask1 = ~(pkt->get<uint8_t>());
165        if ((picr & mask1) && !picInterrupting) {
166            picInterrupting = true;
167            tsunami->cchip->postDRIR(55);
168            DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
169        }
170        if ((!(picr & mask1)) && picInterrupting) {
171            picInterrupting = false;
172            tsunami->cchip->clearDRIR(55);
173            DPRINTF(Tsunami, "clearing pic interrupt\n");
174        }
175        break;
176      case TSDEV_PIC2_MASK:
177        mask2 = pkt->get<uint8_t>();
178        //PIC2 Not implemented to interrupt
179        break;
180      case TSDEV_PIC1_ACK:
181        // clear the interrupt on the PIC
182        picr &= ~(1 << (pkt->get<uint8_t>() & 0xF));
183        if (!(picr & mask1))
184            tsunami->cchip->clearDRIR(55);
185        break;
186      case TSDEV_DMA1_MODE:
187        mode1 = pkt->get<uint8_t>();
188        break;
189      case TSDEV_DMA2_MODE:
190        mode2 = pkt->get<uint8_t>();
191        break;
192      case TSDEV_TMR0_DATA:
193        pitimer.writeCounter(0, pkt->get<uint8_t>());
194        break;
195      case TSDEV_TMR1_DATA:
196        pitimer.writeCounter(1, pkt->get<uint8_t>());
197        break;
198      case TSDEV_TMR2_DATA:
199        pitimer.writeCounter(2, pkt->get<uint8_t>());
200        break;
201      case TSDEV_TMR_CTRL:
202        pitimer.writeControl(pkt->get<uint8_t>());
203        break;
204      case TSDEV_RTC_ADDR:
205        rtcAddr = pkt->get<uint8_t>();
206        break;
207      case TSDEV_RTC_DATA:
208        rtc.writeData(rtcAddr, pkt->get<uint8_t>());
209        break;
210      case TSDEV_KBD:
211      case TSDEV_DMA1_CMND:
212      case TSDEV_DMA2_CMND:
213      case TSDEV_DMA1_MMASK:
214      case TSDEV_DMA2_MMASK:
215      case TSDEV_PIC2_ACK:
216      case TSDEV_DMA1_RESET:
217      case TSDEV_DMA2_RESET:
218      case TSDEV_DMA1_MASK:
219      case TSDEV_DMA2_MASK:
220      case TSDEV_CTRL_PORTB:
221        break;
222      default:
223        panic("I/O Write - va%#x size %d data %#x\n", pkt->getAddr(), pkt->getSize(), pkt->get<uint8_t>());
224    }
225
226    pkt->makeAtomicResponse();
227    return pioDelay;
228}
229
230void
231TsunamiIO::postPIC(uint8_t bitvector)
232{
233    //PIC2 Is not implemented, because nothing of interest there
234    picr |= bitvector;
235    if (picr & mask1) {
236        tsunami->cchip->postDRIR(55);
237        DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
238    }
239}
240
241void
242TsunamiIO::clearPIC(uint8_t bitvector)
243{
244    //PIC2 Is not implemented, because nothing of interest there
245    picr &= ~bitvector;
246    if (!(picr & mask1)) {
247        tsunami->cchip->clearDRIR(55);
248        DPRINTF(Tsunami, "clearing pic interrupt to cchip\n");
249    }
250}
251
252void
253TsunamiIO::serialize(ostream &os)
254{
255    SERIALIZE_SCALAR(rtcAddr);
256    SERIALIZE_SCALAR(timerData);
257    SERIALIZE_SCALAR(mask1);
258    SERIALIZE_SCALAR(mask2);
259    SERIALIZE_SCALAR(mode1);
260    SERIALIZE_SCALAR(mode2);
261    SERIALIZE_SCALAR(picr);
262    SERIALIZE_SCALAR(picInterrupting);
263
264    // Serialize the timers
265    pitimer.serialize("pitimer", os);
266    rtc.serialize("rtc", os);
267}
268
269void
270TsunamiIO::unserialize(Checkpoint *cp, const string &section)
271{
272    UNSERIALIZE_SCALAR(rtcAddr);
273    UNSERIALIZE_SCALAR(timerData);
274    UNSERIALIZE_SCALAR(mask1);
275    UNSERIALIZE_SCALAR(mask2);
276    UNSERIALIZE_SCALAR(mode1);
277    UNSERIALIZE_SCALAR(mode2);
278    UNSERIALIZE_SCALAR(picr);
279    UNSERIALIZE_SCALAR(picInterrupting);
280
281    // Unserialize the timers
282    pitimer.unserialize("pitimer", cp, section);
283    rtc.unserialize("rtc", cp, section);
284}
285
286TsunamiIO *
287TsunamiIOParams::create()
288{
289    return new TsunamiIO(this);
290}
291