tsunami_io.cc revision 5606
1803SN/A/* 21363SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 3803SN/A * All rights reserved. 4803SN/A * 5803SN/A * Redistribution and use in source and binary forms, with or without 6803SN/A * modification, are permitted provided that the following conditions are 7803SN/A * met: redistributions of source code must retain the above copyright 8803SN/A * notice, this list of conditions and the following disclaimer; 9803SN/A * redistributions in binary form must reproduce the above copyright 10803SN/A * notice, this list of conditions and the following disclaimer in the 11803SN/A * documentation and/or other materials provided with the distribution; 12803SN/A * neither the name of the copyright holders nor the names of its 13803SN/A * contributors may be used to endorse or promote products derived from 14803SN/A * this software without specific prior written permission. 15803SN/A * 16803SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17803SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18803SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19803SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20803SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21803SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22803SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23803SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24803SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25803SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26803SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Ali Saidi 292665SN/A * Andrew Schultz 302665SN/A * Miguel Serrano 31803SN/A */ 32768SN/A 331730SN/A/** @file 34773SN/A * Tsunami I/O including PIC, PIT, RTC, DMA 35768SN/A */ 36768SN/A 37773SN/A#include <sys/time.h> 38773SN/A 39768SN/A#include <deque> 40768SN/A#include <string> 41768SN/A#include <vector> 42768SN/A 434762Snate@binkert.org#include "base/time.hh" 44768SN/A#include "base/trace.hh" 452542SN/A#include "dev/rtcreg.h" 463540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_cchip.hh" 473540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami.hh" 483540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_io.hh" 493540Sgblack@eecs.umich.edu#include "dev/alpha/tsunamireg.h" 503348SN/A#include "mem/packet.hh" 513348SN/A#include "mem/packet_access.hh" 522542SN/A#include "mem/port.hh" 532542SN/A#include "sim/system.hh" 54768SN/A 55768SN/Ausing namespace std; 562107SN/A//Should this be AlphaISA? 572107SN/Ausing namespace TheISA; 58773SN/A 595606Snate@binkert.orgTsunamiIO::RTC::RTC(const string &n, const TsunamiIOParams *p) 605606Snate@binkert.org : MC146818(p->tsunami, n, p->time, p->year_is_bcd, p->frequency), 615606Snate@binkert.org tsunami(p->tsunami) 621817SN/A{ 63772SN/A} 64772SN/A 654762Snate@binkert.orgTsunamiIO::TsunamiIO(const Params *p) 665606Snate@binkert.org : BasicPioDevice(p), tsunami(p->tsunami), 675606Snate@binkert.org pitimer(this, p->name + "pitimer"), rtc(p->name + ".rtc", p) 68768SN/A{ 693846Shsul@eecs.umich.edu pioSize = 0x100; 70909SN/A 71803SN/A // set the back pointer from tsunami to myself 72803SN/A tsunami->io = this; 73803SN/A 74771SN/A timerData = 0; 75777SN/A picr = 0; 76777SN/A picInterrupting = false; 77773SN/A} 78773SN/A 791634SN/ATick 801634SN/ATsunamiIO::frequency() const 811634SN/A{ 822539SN/A return Clock::Frequency / params()->frequency; 831634SN/A} 841634SN/A 852542SN/ATick 863349SN/ATsunamiIO::read(PacketPtr pkt) 87768SN/A{ 882641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 89768SN/A 902641SN/A Addr daddr = pkt->getAddr() - pioAddr; 91865SN/A 922641SN/A DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(), 932641SN/A pkt->getSize(), daddr); 94771SN/A 952630SN/A pkt->allocate(); 962539SN/A 972641SN/A if (pkt->getSize() == sizeof(uint8_t)) { 98803SN/A switch(daddr) { 991817SN/A // PIC1 mask read 1001817SN/A case TSDEV_PIC1_MASK: 1012630SN/A pkt->set(~mask1); 1022539SN/A break; 1031817SN/A case TSDEV_PIC2_MASK: 1042630SN/A pkt->set(~mask2); 1052539SN/A break; 106865SN/A case TSDEV_PIC1_ISR: 107865SN/A // !!! If this is modified 64bit case needs to be too 108865SN/A // Pal code has to do a 64 bit physical read because there is 109865SN/A // no load physical byte instruction 1102630SN/A pkt->set(picr); 1112539SN/A break; 112865SN/A case TSDEV_PIC2_ISR: 113865SN/A // PIC2 not implemnted... just return 0 1142630SN/A pkt->set(0x00); 1152539SN/A break; 1161817SN/A case TSDEV_TMR0_DATA: 1172648SN/A pkt->set(pitimer.counter0.read()); 1182542SN/A break; 1191817SN/A case TSDEV_TMR1_DATA: 1202648SN/A pkt->set(pitimer.counter1.read()); 1212542SN/A break; 1221817SN/A case TSDEV_TMR2_DATA: 1232648SN/A pkt->set(pitimer.counter2.read()); 1242539SN/A break; 125803SN/A case TSDEV_RTC_DATA: 1265392Sgblack@eecs.umich.edu pkt->set(rtc.readData(rtcAddr)); 1272539SN/A break; 1281817SN/A case TSDEV_CTRL_PORTB: 1291817SN/A if (pitimer.counter2.outputHigh()) 1302630SN/A pkt->set(PORTB_SPKR_HIGH); 1311817SN/A else 1322630SN/A pkt->set(0x00); 1332539SN/A break; 134803SN/A default: 1352641SN/A panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize()); 136803SN/A } 1372641SN/A } else if (pkt->getSize() == sizeof(uint64_t)) { 1382539SN/A if (daddr == TSDEV_PIC1_ISR) 1392630SN/A pkt->set<uint64_t>(picr); 1402539SN/A else 1412539SN/A panic("I/O Read - invalid addr - va %#x size %d\n", 1422641SN/A pkt->getAddr(), pkt->getSize()); 1432539SN/A } else { 1442641SN/A panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize()); 145771SN/A } 1464870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 1472539SN/A return pioDelay; 148768SN/A} 149768SN/A 1502539SN/ATick 1513349SN/ATsunamiIO::write(PacketPtr pkt) 152768SN/A{ 1532641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1542641SN/A Addr daddr = pkt->getAddr() - pioAddr; 155779SN/A 156779SN/A DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n", 1572641SN/A pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff, (uint32_t)pkt->get<uint8_t>()); 158768SN/A 1592641SN/A assert(pkt->getSize() == sizeof(uint8_t)); 160769SN/A 1612539SN/A switch(daddr) { 1622539SN/A case TSDEV_PIC1_MASK: 1632630SN/A mask1 = ~(pkt->get<uint8_t>()); 1642539SN/A if ((picr & mask1) && !picInterrupting) { 1652539SN/A picInterrupting = true; 1662539SN/A tsunami->cchip->postDRIR(55); 1672539SN/A DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); 168803SN/A } 1692539SN/A if ((!(picr & mask1)) && picInterrupting) { 1702539SN/A picInterrupting = false; 1712539SN/A tsunami->cchip->clearDRIR(55); 1722539SN/A DPRINTF(Tsunami, "clearing pic interrupt\n"); 1732539SN/A } 1742539SN/A break; 1752539SN/A case TSDEV_PIC2_MASK: 1762630SN/A mask2 = pkt->get<uint8_t>(); 1772539SN/A //PIC2 Not implemented to interrupt 1782539SN/A break; 1792539SN/A case TSDEV_PIC1_ACK: 1802539SN/A // clear the interrupt on the PIC 1812630SN/A picr &= ~(1 << (pkt->get<uint8_t>() & 0xF)); 1822539SN/A if (!(picr & mask1)) 1832539SN/A tsunami->cchip->clearDRIR(55); 1842539SN/A break; 1852539SN/A case TSDEV_DMA1_MODE: 1862630SN/A mode1 = pkt->get<uint8_t>(); 1872539SN/A break; 1882539SN/A case TSDEV_DMA2_MODE: 1892630SN/A mode2 = pkt->get<uint8_t>(); 1902539SN/A break; 1912539SN/A case TSDEV_TMR0_DATA: 1922630SN/A pitimer.counter0.write(pkt->get<uint8_t>()); 1932539SN/A break; 1942539SN/A case TSDEV_TMR1_DATA: 1952630SN/A pitimer.counter1.write(pkt->get<uint8_t>()); 1962539SN/A break; 1972539SN/A case TSDEV_TMR2_DATA: 1982630SN/A pitimer.counter2.write(pkt->get<uint8_t>()); 1992539SN/A break; 2002539SN/A case TSDEV_TMR_CTRL: 2012630SN/A pitimer.writeControl(pkt->get<uint8_t>()); 2022539SN/A break; 2032539SN/A case TSDEV_RTC_ADDR: 2045392Sgblack@eecs.umich.edu rtcAddr = pkt->get<uint8_t>(); 2052539SN/A break; 2062539SN/A case TSDEV_RTC_DATA: 2075392Sgblack@eecs.umich.edu rtc.writeData(rtcAddr, pkt->get<uint8_t>()); 2082539SN/A break; 2092539SN/A case TSDEV_KBD: 2102539SN/A case TSDEV_DMA1_CMND: 2112539SN/A case TSDEV_DMA2_CMND: 2122539SN/A case TSDEV_DMA1_MMASK: 2132539SN/A case TSDEV_DMA2_MMASK: 2142539SN/A case TSDEV_PIC2_ACK: 2152539SN/A case TSDEV_DMA1_RESET: 2162539SN/A case TSDEV_DMA2_RESET: 2172539SN/A case TSDEV_DMA1_MASK: 2182539SN/A case TSDEV_DMA2_MASK: 2192539SN/A case TSDEV_CTRL_PORTB: 2202539SN/A break; 221803SN/A default: 2222641SN/A panic("I/O Write - va%#x size %d data %#x\n", pkt->getAddr(), pkt->getSize(), pkt->get<uint8_t>()); 223769SN/A } 224769SN/A 2254870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 2262539SN/A return pioDelay; 227768SN/A} 228768SN/A 229768SN/Avoid 230777SN/ATsunamiIO::postPIC(uint8_t bitvector) 231777SN/A{ 232777SN/A //PIC2 Is not implemented, because nothing of interest there 233777SN/A picr |= bitvector; 234865SN/A if (picr & mask1) { 235817SN/A tsunami->cchip->postDRIR(55); 236777SN/A DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); 237777SN/A } 238777SN/A} 239777SN/A 240777SN/Avoid 241777SN/ATsunamiIO::clearPIC(uint8_t bitvector) 242777SN/A{ 243777SN/A //PIC2 Is not implemented, because nothing of interest there 244777SN/A picr &= ~bitvector; 245777SN/A if (!(picr & mask1)) { 246817SN/A tsunami->cchip->clearDRIR(55); 247777SN/A DPRINTF(Tsunami, "clearing pic interrupt to cchip\n"); 248777SN/A } 249777SN/A} 250777SN/A 251777SN/Avoid 2521854SN/ATsunamiIO::serialize(ostream &os) 253768SN/A{ 2545392Sgblack@eecs.umich.edu SERIALIZE_SCALAR(rtcAddr); 255811SN/A SERIALIZE_SCALAR(timerData); 256899SN/A SERIALIZE_SCALAR(mask1); 257899SN/A SERIALIZE_SCALAR(mask2); 258899SN/A SERIALIZE_SCALAR(mode1); 259899SN/A SERIALIZE_SCALAR(mode2); 260811SN/A SERIALIZE_SCALAR(picr); 261811SN/A SERIALIZE_SCALAR(picInterrupting); 262811SN/A 263919SN/A // Serialize the timers 2641854SN/A pitimer.serialize("pitimer", os); 2651854SN/A rtc.serialize("rtc", os); 266768SN/A} 267768SN/A 268768SN/Avoid 2691854SN/ATsunamiIO::unserialize(Checkpoint *cp, const string §ion) 270768SN/A{ 2715392Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(rtcAddr); 272811SN/A UNSERIALIZE_SCALAR(timerData); 273899SN/A UNSERIALIZE_SCALAR(mask1); 274899SN/A UNSERIALIZE_SCALAR(mask2); 275899SN/A UNSERIALIZE_SCALAR(mode1); 276899SN/A UNSERIALIZE_SCALAR(mode2); 277811SN/A UNSERIALIZE_SCALAR(picr); 278811SN/A UNSERIALIZE_SCALAR(picInterrupting); 279919SN/A 280919SN/A // Unserialize the timers 2811854SN/A pitimer.unserialize("pitimer", cp, section); 2821854SN/A rtc.unserialize("rtc", cp, section); 283768SN/A} 284768SN/A 2854762Snate@binkert.orgTsunamiIO * 2864762Snate@binkert.orgTsunamiIOParams::create() 287768SN/A{ 2884762Snate@binkert.org return new TsunamiIO(this); 289768SN/A} 290