tsunami_cchip.hh revision 11168:f98eb2da15a4 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/** @file
32 * Emulation of the Tsunami CChip CSRs
33 */
34
35#ifndef __TSUNAMI_CCHIP_HH__
36#define __TSUNAMI_CCHIP_HH__
37
38#include "dev/alpha/tsunami.hh"
39#include "dev/io_device.hh"
40#include "params/TsunamiCChip.hh"
41
42/**
43 * Tsunami CChip CSR Emulation. This device includes all the interrupt
44 * handling code for the chipset.
45 */
46class TsunamiCChip : public BasicPioDevice
47{
48  protected:
49    /**
50     * pointer to the tsunami object.
51     * This is our access to all the other tsunami
52     * devices.
53     */
54    Tsunami *tsunami;
55
56    /**
57     * The dims are device interrupt mask registers.
58     * One exists for each CPU, the DRIR X DIM = DIR
59     */
60    uint64_t dim[Tsunami::Max_CPUs];
61
62    /**
63     * The dirs are device interrupt registers.
64     * One exists for each CPU, the DRIR X DIM = DIR
65     */
66    uint64_t dir[Tsunami::Max_CPUs];
67
68    /**
69     * This register contains bits for each PCI interrupt
70     * that can occur.
71     */
72    uint64_t drir;
73
74    /** Indicator of which CPUs have an IPI interrupt */
75    uint64_t ipint;
76
77    /** Indicator of which CPUs have an RTC interrupt */
78    uint64_t itint;
79
80  public:
81    typedef TsunamiCChipParams Params;
82    /**
83     * Initialize the Tsunami CChip by setting all of the
84     * device register to 0.
85     * @param p params struct
86     */
87    TsunamiCChip(const Params *p);
88
89    const Params *
90    params() const
91    {
92        return dynamic_cast<const Params *>(_params);
93    }
94
95    virtual Tick read(PacketPtr pkt);
96
97    virtual Tick write(PacketPtr pkt);
98
99    /**
100     * post an RTC interrupt to the CPU
101     */
102    void postRTC();
103
104    /**
105     * post an interrupt to the CPU.
106     * @param interrupt the interrupt number to post (0-64)
107     */
108    void postDRIR(uint32_t interrupt);
109
110    /**
111     * clear an interrupt previously posted to the CPU.
112     * @param interrupt the interrupt number to post (0-64)
113     */
114    void clearDRIR(uint32_t interrupt);
115
116    /**
117     * post an ipi interrupt  to the CPU.
118     * @param ipintr the cpu number to clear(bitvector)
119     */
120    void clearIPI(uint64_t ipintr);
121
122    /**
123     * clear a timer interrupt previously posted to the CPU.
124     * @param itintr the cpu number to clear(bitvector)
125     */
126    void clearITI(uint64_t itintr);
127
128    /**
129     * request an interrupt be posted to the CPU.
130     * @param ipreq the cpu number to interrupt(bitvector)
131     */
132    void reqIPI(uint64_t ipreq);
133
134    void serialize(CheckpointOut &cp) const override;
135    void unserialize(CheckpointIn &cp) override;
136};
137
138#endif // __TSUNAMI_CCHIP_HH__
139