tsunami_cchip.hh revision 11168:f98eb2da15a4
17977Shsul@eecs.umich.edu/*
28008Ssaidi@eecs.umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan
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278003Ssaidi@eecs.umich.edu *
288008Ssaidi@eecs.umich.edu * Authors: Ali Saidi
298003Ssaidi@eecs.umich.edu */
308003Ssaidi@eecs.umich.edu
318008Ssaidi@eecs.umich.edu/** @file
327977Shsul@eecs.umich.edu * Emulation of the Tsunami CChip CSRs
337977Shsul@eecs.umich.edu */
348008Ssaidi@eecs.umich.edu
357977Shsul@eecs.umich.edu#ifndef __TSUNAMI_CCHIP_HH__
368008Ssaidi@eecs.umich.edu#define __TSUNAMI_CCHIP_HH__
378008Ssaidi@eecs.umich.edu
387977Shsul@eecs.umich.edu#include "dev/alpha/tsunami.hh"
398008Ssaidi@eecs.umich.edu#include "dev/io_device.hh"
408008Ssaidi@eecs.umich.edu#include "params/TsunamiCChip.hh"
417977Shsul@eecs.umich.edu
427981Sbinkertn@umich.edu/**
437981Sbinkertn@umich.edu * Tsunami CChip CSR Emulation. This device includes all the interrupt
447981Sbinkertn@umich.edu * handling code for the chipset.
457977Shsul@eecs.umich.edu */
468008Ssaidi@eecs.umich.educlass TsunamiCChip : public BasicPioDevice
47{
48  protected:
49    /**
50     * pointer to the tsunami object.
51     * This is our access to all the other tsunami
52     * devices.
53     */
54    Tsunami *tsunami;
55
56    /**
57     * The dims are device interrupt mask registers.
58     * One exists for each CPU, the DRIR X DIM = DIR
59     */
60    uint64_t dim[Tsunami::Max_CPUs];
61
62    /**
63     * The dirs are device interrupt registers.
64     * One exists for each CPU, the DRIR X DIM = DIR
65     */
66    uint64_t dir[Tsunami::Max_CPUs];
67
68    /**
69     * This register contains bits for each PCI interrupt
70     * that can occur.
71     */
72    uint64_t drir;
73
74    /** Indicator of which CPUs have an IPI interrupt */
75    uint64_t ipint;
76
77    /** Indicator of which CPUs have an RTC interrupt */
78    uint64_t itint;
79
80  public:
81    typedef TsunamiCChipParams Params;
82    /**
83     * Initialize the Tsunami CChip by setting all of the
84     * device register to 0.
85     * @param p params struct
86     */
87    TsunamiCChip(const Params *p);
88
89    const Params *
90    params() const
91    {
92        return dynamic_cast<const Params *>(_params);
93    }
94
95    virtual Tick read(PacketPtr pkt);
96
97    virtual Tick write(PacketPtr pkt);
98
99    /**
100     * post an RTC interrupt to the CPU
101     */
102    void postRTC();
103
104    /**
105     * post an interrupt to the CPU.
106     * @param interrupt the interrupt number to post (0-64)
107     */
108    void postDRIR(uint32_t interrupt);
109
110    /**
111     * clear an interrupt previously posted to the CPU.
112     * @param interrupt the interrupt number to post (0-64)
113     */
114    void clearDRIR(uint32_t interrupt);
115
116    /**
117     * post an ipi interrupt  to the CPU.
118     * @param ipintr the cpu number to clear(bitvector)
119     */
120    void clearIPI(uint64_t ipintr);
121
122    /**
123     * clear a timer interrupt previously posted to the CPU.
124     * @param itintr the cpu number to clear(bitvector)
125     */
126    void clearITI(uint64_t itintr);
127
128    /**
129     * request an interrupt be posted to the CPU.
130     * @param ipreq the cpu number to interrupt(bitvector)
131     */
132    void reqIPI(uint64_t ipreq);
133
134    void serialize(CheckpointOut &cp) const override;
135    void unserialize(CheckpointIn &cp) override;
136};
137
138#endif // __TSUNAMI_CCHIP_HH__
139