tsunami_cchip.hh revision 11168:f98eb2da15a4
18981Sandreas.hansson@arm.com/* 28981Sandreas.hansson@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 38981Sandreas.hansson@arm.com * All rights reserved. 48981Sandreas.hansson@arm.com * 58981Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68981Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78981Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88981Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98981Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108981Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118981Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128981Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138981Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 148981Sandreas.hansson@arm.com * this software without specific prior written permission. 158981Sandreas.hansson@arm.com * 168981Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 178981Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 188981Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 198981Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208981Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218981Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 228981Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 238981Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 248981Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 258981Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 268981Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 278981Sandreas.hansson@arm.com * 288981Sandreas.hansson@arm.com * Authors: Ali Saidi 298981Sandreas.hansson@arm.com */ 308981Sandreas.hansson@arm.com 318981Sandreas.hansson@arm.com/** @file 328981Sandreas.hansson@arm.com * Emulation of the Tsunami CChip CSRs 338981Sandreas.hansson@arm.com */ 348981Sandreas.hansson@arm.com 358981Sandreas.hansson@arm.com#ifndef __TSUNAMI_CCHIP_HH__ 368981Sandreas.hansson@arm.com#define __TSUNAMI_CCHIP_HH__ 378981Sandreas.hansson@arm.com 388981Sandreas.hansson@arm.com#include "dev/alpha/tsunami.hh" 398981Sandreas.hansson@arm.com#include "dev/io_device.hh" 408981Sandreas.hansson@arm.com#include "params/TsunamiCChip.hh" 418981Sandreas.hansson@arm.com 428981Sandreas.hansson@arm.com/** 438981Sandreas.hansson@arm.com * Tsunami CChip CSR Emulation. This device includes all the interrupt 448981Sandreas.hansson@arm.com * handling code for the chipset. 458981Sandreas.hansson@arm.com */ 468981Sandreas.hansson@arm.comclass TsunamiCChip : public BasicPioDevice 478981Sandreas.hansson@arm.com{ 488981Sandreas.hansson@arm.com protected: 498981Sandreas.hansson@arm.com /** 508981Sandreas.hansson@arm.com * pointer to the tsunami object. 518981Sandreas.hansson@arm.com * This is our access to all the other tsunami 528981Sandreas.hansson@arm.com * devices. 538981Sandreas.hansson@arm.com */ 548981Sandreas.hansson@arm.com Tsunami *tsunami; 558981Sandreas.hansson@arm.com 568981Sandreas.hansson@arm.com /** 578981Sandreas.hansson@arm.com * The dims are device interrupt mask registers. 588981Sandreas.hansson@arm.com * One exists for each CPU, the DRIR X DIM = DIR 598981Sandreas.hansson@arm.com */ 608981Sandreas.hansson@arm.com uint64_t dim[Tsunami::Max_CPUs]; 618981Sandreas.hansson@arm.com 628981Sandreas.hansson@arm.com /** 638981Sandreas.hansson@arm.com * The dirs are device interrupt registers. 648981Sandreas.hansson@arm.com * One exists for each CPU, the DRIR X DIM = DIR 658981Sandreas.hansson@arm.com */ 668981Sandreas.hansson@arm.com uint64_t dir[Tsunami::Max_CPUs]; 678981Sandreas.hansson@arm.com 688981Sandreas.hansson@arm.com /** 698981Sandreas.hansson@arm.com * This register contains bits for each PCI interrupt 708981Sandreas.hansson@arm.com * that can occur. 718981Sandreas.hansson@arm.com */ 728981Sandreas.hansson@arm.com uint64_t drir; 738981Sandreas.hansson@arm.com 748981Sandreas.hansson@arm.com /** Indicator of which CPUs have an IPI interrupt */ 758981Sandreas.hansson@arm.com uint64_t ipint; 768981Sandreas.hansson@arm.com 778981Sandreas.hansson@arm.com /** Indicator of which CPUs have an RTC interrupt */ 788981Sandreas.hansson@arm.com uint64_t itint; 798981Sandreas.hansson@arm.com 808981Sandreas.hansson@arm.com public: 818981Sandreas.hansson@arm.com typedef TsunamiCChipParams Params; 828981Sandreas.hansson@arm.com /** 838981Sandreas.hansson@arm.com * Initialize the Tsunami CChip by setting all of the 848981Sandreas.hansson@arm.com * device register to 0. 858981Sandreas.hansson@arm.com * @param p params struct 868981Sandreas.hansson@arm.com */ 878981Sandreas.hansson@arm.com TsunamiCChip(const Params *p); 888981Sandreas.hansson@arm.com 898981Sandreas.hansson@arm.com const Params * 908981Sandreas.hansson@arm.com params() const 918981Sandreas.hansson@arm.com { 928981Sandreas.hansson@arm.com return dynamic_cast<const Params *>(_params); 938981Sandreas.hansson@arm.com } 948981Sandreas.hansson@arm.com 958981Sandreas.hansson@arm.com virtual Tick read(PacketPtr pkt); 968981Sandreas.hansson@arm.com 978981Sandreas.hansson@arm.com virtual Tick write(PacketPtr pkt); 988981Sandreas.hansson@arm.com 998981Sandreas.hansson@arm.com /** 1008981Sandreas.hansson@arm.com * post an RTC interrupt to the CPU 1018981Sandreas.hansson@arm.com */ 1028981Sandreas.hansson@arm.com void postRTC(); 1038981Sandreas.hansson@arm.com 1048981Sandreas.hansson@arm.com /** 1058981Sandreas.hansson@arm.com * post an interrupt to the CPU. 1068981Sandreas.hansson@arm.com * @param interrupt the interrupt number to post (0-64) 1078981Sandreas.hansson@arm.com */ 1088981Sandreas.hansson@arm.com void postDRIR(uint32_t interrupt); 1098981Sandreas.hansson@arm.com 1108981Sandreas.hansson@arm.com /** 1118981Sandreas.hansson@arm.com * clear an interrupt previously posted to the CPU. 1128981Sandreas.hansson@arm.com * @param interrupt the interrupt number to post (0-64) 1138981Sandreas.hansson@arm.com */ 1148981Sandreas.hansson@arm.com void clearDRIR(uint32_t interrupt); 1158981Sandreas.hansson@arm.com 1168981Sandreas.hansson@arm.com /** 1178981Sandreas.hansson@arm.com * post an ipi interrupt to the CPU. 1188981Sandreas.hansson@arm.com * @param ipintr the cpu number to clear(bitvector) 1198981Sandreas.hansson@arm.com */ 1208981Sandreas.hansson@arm.com void clearIPI(uint64_t ipintr); 1218981Sandreas.hansson@arm.com 1228981Sandreas.hansson@arm.com /** 1238981Sandreas.hansson@arm.com * clear a timer interrupt previously posted to the CPU. 1248981Sandreas.hansson@arm.com * @param itintr the cpu number to clear(bitvector) 1258981Sandreas.hansson@arm.com */ 1268981Sandreas.hansson@arm.com void clearITI(uint64_t itintr); 1278981Sandreas.hansson@arm.com 1288981Sandreas.hansson@arm.com /** 1298981Sandreas.hansson@arm.com * request an interrupt be posted to the CPU. 1308981Sandreas.hansson@arm.com * @param ipreq the cpu number to interrupt(bitvector) 1318981Sandreas.hansson@arm.com */ 1328981Sandreas.hansson@arm.com void reqIPI(uint64_t ipreq); 1338981Sandreas.hansson@arm.com 1348981Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 1358981Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1368981Sandreas.hansson@arm.com}; 1378981Sandreas.hansson@arm.com 1388981Sandreas.hansson@arm.com#endif // __TSUNAMI_CCHIP_HH__ 1398981Sandreas.hansson@arm.com