tsunami_cchip.hh revision 909
112655Sandreas.sandberg@arm.com/* 212655Sandreas.sandberg@arm.com * Copyright (c) 2004 The Regents of The University of Michigan 312655Sandreas.sandberg@arm.com * All rights reserved. 412655Sandreas.sandberg@arm.com * 512655Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 612655Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 712655Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 812655Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 912655Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1012655Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 1112655Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 1212655Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 1312655Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 1412655Sandreas.sandberg@arm.com * this software without specific prior written permission. 1512655Sandreas.sandberg@arm.com * 1612655Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712655Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812655Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912655Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012655Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112655Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212655Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312655Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412655Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512655Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612655Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712655Sandreas.sandberg@arm.com */ 2812655Sandreas.sandberg@arm.com 2912655Sandreas.sandberg@arm.com/* @file 3012655Sandreas.sandberg@arm.com * Emulation of the Tsunami CChip CSRs 3112655Sandreas.sandberg@arm.com */ 3212655Sandreas.sandberg@arm.com 3312655Sandreas.sandberg@arm.com#ifndef __TSUNAMI_CCHIP_HH__ 3412655Sandreas.sandberg@arm.com#define __TSUNAMI_CCHIP_HH__ 3512655Sandreas.sandberg@arm.com 3612655Sandreas.sandberg@arm.com#include "dev/tsunami.hh" 3712655Sandreas.sandberg@arm.com#include "base/range.hh" 3812655Sandreas.sandberg@arm.com#include "dev/io_device.hh" 3912655Sandreas.sandberg@arm.com 4012655Sandreas.sandberg@arm.com/* 4112655Sandreas.sandberg@arm.com * Tsunami CChip 4212655Sandreas.sandberg@arm.com */ 4312655Sandreas.sandberg@arm.comclass TsunamiCChip : public PioDevice 4412655Sandreas.sandberg@arm.com{ 4512655Sandreas.sandberg@arm.com private: 4612655Sandreas.sandberg@arm.com /** The base address of this device */ 4712655Sandreas.sandberg@arm.com Addr addr; 4812655Sandreas.sandberg@arm.com 4912655Sandreas.sandberg@arm.com /** The size of mappad from the above address */ 5012655Sandreas.sandberg@arm.com static const Addr size = 0xfff; 5112655Sandreas.sandberg@arm.com 5212655Sandreas.sandberg@arm.com protected: 5312655Sandreas.sandberg@arm.com /** 5412655Sandreas.sandberg@arm.com * pointer to the tsunami object. 5512655Sandreas.sandberg@arm.com * This is our access to all the other tsunami 5612655Sandreas.sandberg@arm.com * devices. 5712655Sandreas.sandberg@arm.com */ 5812655Sandreas.sandberg@arm.com Tsunami *tsunami; 5912655Sandreas.sandberg@arm.com 6012655Sandreas.sandberg@arm.com /** 6112655Sandreas.sandberg@arm.com * The dims are device interrupt mask registers. 6212655Sandreas.sandberg@arm.com * One exists for each CPU, the DRIR X DIM = DIR 6312655Sandreas.sandberg@arm.com */ 6412655Sandreas.sandberg@arm.com uint64_t dim[Tsunami::Max_CPUs]; 6512655Sandreas.sandberg@arm.com 6612655Sandreas.sandberg@arm.com /** 6712655Sandreas.sandberg@arm.com * The dirs are device interrupt registers. 6812655Sandreas.sandberg@arm.com * One exists for each CPU, the DRIR X DIM = DIR 6912655Sandreas.sandberg@arm.com */ 7012655Sandreas.sandberg@arm.com uint64_t dir[Tsunami::Max_CPUs]; 7112655Sandreas.sandberg@arm.com bool dirInterrupting[Tsunami::Max_CPUs]; 7212655Sandreas.sandberg@arm.com 7312655Sandreas.sandberg@arm.com /** 7412655Sandreas.sandberg@arm.com * This register contains bits for each PCI interrupt 7512655Sandreas.sandberg@arm.com * that can occur. 7612655Sandreas.sandberg@arm.com */ 7712655Sandreas.sandberg@arm.com uint64_t drir; 7812655Sandreas.sandberg@arm.com 7912656Sandreas.sandberg@arm.com /** 8012656Sandreas.sandberg@arm.com * The MISC register contains the CPU we are currently on 8112655Sandreas.sandberg@arm.com * as well as bits to ack RTC and IPI interrupts. 8212656Sandreas.sandberg@arm.com */ 8312655Sandreas.sandberg@arm.com uint64_t misc; 8412655Sandreas.sandberg@arm.com 8512655Sandreas.sandberg@arm.com /** Count of the number of pending IPIs on a CPU */ 8612656Sandreas.sandberg@arm.com uint64_t ipiInterrupting[Tsunami::Max_CPUs]; 8712655Sandreas.sandberg@arm.com 8812655Sandreas.sandberg@arm.com /** Indicator of which CPUs have had an RTC interrupt */ 8912655Sandreas.sandberg@arm.com bool RTCInterrupting[Tsunami::Max_CPUs]; 9012655Sandreas.sandberg@arm.com 9112655Sandreas.sandberg@arm.com public: 9212656Sandreas.sandberg@arm.com /** 9312655Sandreas.sandberg@arm.com * Initialize the Tsunami CChip by setting all of the 9412655Sandreas.sandberg@arm.com * device register to 0. 9512655Sandreas.sandberg@arm.com * @param name name of this device. 9612655Sandreas.sandberg@arm.com * @param t pointer back to the Tsunami object that we belong to. 9712656Sandreas.sandberg@arm.com * @param a address we are mapped at. 9812655Sandreas.sandberg@arm.com * @param mmu pointer to the memory controller that sends us events. 9912655Sandreas.sandberg@arm.com * @param hier object to store parameters universal the device hierarchy 10012655Sandreas.sandberg@arm.com * @param bus The bus that this device is attached to 10112655Sandreas.sandberg@arm.com */ 10212655Sandreas.sandberg@arm.com TsunamiCChip(const std::string &name, Tsunami *t, Addr a, 10312655Sandreas.sandberg@arm.com MemoryController *mmu, HierParams *hier, Bus *bus); 10412655Sandreas.sandberg@arm.com 10512655Sandreas.sandberg@arm.com /** 10612656Sandreas.sandberg@arm.com * Process a read to the CChip. 10712655Sandreas.sandberg@arm.com * @param req Contains the address to read from. 10812655Sandreas.sandberg@arm.com * @param data A pointer to write the read data to. 10912655Sandreas.sandberg@arm.com * @return The fault condition of the access. 11012655Sandreas.sandberg@arm.com */ 11112655Sandreas.sandberg@arm.com virtual Fault read(MemReqPtr &req, uint8_t *data); 11212655Sandreas.sandberg@arm.com 11312655Sandreas.sandberg@arm.com 11412656Sandreas.sandberg@arm.com /** 11512655Sandreas.sandberg@arm.com * Process a write to the CChip. 11612655Sandreas.sandberg@arm.com * @param req Contains the address to write to. 11712655Sandreas.sandberg@arm.com * @param data The data to write. 11812655Sandreas.sandberg@arm.com * @return The fault condition of the access. 11912655Sandreas.sandberg@arm.com */ 12012655Sandreas.sandberg@arm.com virtual Fault write(MemReqPtr &req, const uint8_t *data); 12112656Sandreas.sandberg@arm.com 12212655Sandreas.sandberg@arm.com /** 12312655Sandreas.sandberg@arm.com * post an RTC interrupt to the CPU 12412655Sandreas.sandberg@arm.com */ 12512656Sandreas.sandberg@arm.com void postRTC(); 12612656Sandreas.sandberg@arm.com 12712656Sandreas.sandberg@arm.com /** 12812656Sandreas.sandberg@arm.com * post an interrupt to the CPU. 12912655Sandreas.sandberg@arm.com * @param interrupt the interrupt number to post (0-64) 13012656Sandreas.sandberg@arm.com */ 13112656Sandreas.sandberg@arm.com void postDRIR(uint32_t interrupt); 13212656Sandreas.sandberg@arm.com 13312656Sandreas.sandberg@arm.com /** 13412656Sandreas.sandberg@arm.com * clear an interrupt previously posted to the CPU. 13512656Sandreas.sandberg@arm.com * @param interrupt the interrupt number to post (0-64) 13612656Sandreas.sandberg@arm.com */ 13712655Sandreas.sandberg@arm.com void clearDRIR(uint32_t interrupt); 13812655Sandreas.sandberg@arm.com 13912656Sandreas.sandberg@arm.com /** 14012655Sandreas.sandberg@arm.com * Serialize this object to the given output stream. 14112655Sandreas.sandberg@arm.com * @param os The stream to serialize to. 14212655Sandreas.sandberg@arm.com */ 14312655Sandreas.sandberg@arm.com virtual void serialize(std::ostream &os); 14412655Sandreas.sandberg@arm.com 14512655Sandreas.sandberg@arm.com /** 14612655Sandreas.sandberg@arm.com * Reconstruct the state of this object from a checkpoint. 14712655Sandreas.sandberg@arm.com * @param cp The checkpoint use. 14812655Sandreas.sandberg@arm.com * @param section The section name of this object 14912655Sandreas.sandberg@arm.com */ 15012655Sandreas.sandberg@arm.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 15112655Sandreas.sandberg@arm.com 15212655Sandreas.sandberg@arm.com /** 15312655Sandreas.sandberg@arm.com * Return how long this access will take. 15412655Sandreas.sandberg@arm.com * @param req the memory request to calcuate 15512655Sandreas.sandberg@arm.com * @return Tick when the request is done 15612655Sandreas.sandberg@arm.com */ 15712655Sandreas.sandberg@arm.com Tick cacheAccess(MemReqPtr &req); 15812655Sandreas.sandberg@arm.com}; 15912655Sandreas.sandberg@arm.com 16012655Sandreas.sandberg@arm.com#endif // __TSUNAMI_CCHIP_HH__ 16112655Sandreas.sandberg@arm.com